Signal integrity will matter more in next-generationflash devices, and several changes in thetechnology will make managing signal integritymore critical. For example, data rates in these deviceswill range from 400 MHz to 6 GHz. To supportthe faster data rates, edge rates will have tobecome 10 to 100 times faster. Demand for increased storagecapacity will also drive the need for denser packaging and morecomplex interconnects. Pressure to reduce costs will force youto make trade-offs that affect signal integrity, such as using lower-cost materials or even eliminating the use of ground planes.As rise times become shorter, a signal’s high-frequencycomponents become more pronounced. Higher-frequencysignals are more sensitive to interconnect quality, so signal-integrityproblems tend to proliferate. As signal frequenciesincrease, signal loss also increases. Therefore, high-frequencycomponents of fast-rise-time signals experience more lossthan the low-frequency components, leading to signal distortionand ISI (intersymbol interference).
Understanding the causes of signal-integrity problems andtheir remedies is critical. Signal-integrity problems includereflections and distortions, crosstalk, ground bounce, and jitter.Reflections and distortions relate to signal quality on anindividual net. When a signal encounters an impedance discontinuity,it generates a reflection that becomes further distortedas it continues along the net. The reflection travelsfrom the impedance discontinuity in two directions—towardthe receiver and back to the driver. The reflections themselvesreact to other discontinuities, creating further reflectionsthat distort the true signal in complex ways, generatingeffects such as ringing, overshoot, and slope reversal. Carefuldesign to maintain well-controlled impedance along keytraces is the best way to improve signal integrity.
The quality of grounding and current-return paths in yourdesign is among the biggest factors affecting crosstalk. In mostPCB (printed-circuit-board) designs, ground planes are availableas return paths. This approach is best if you can affordthe extra plane. If cost pressure forces you to eliminate using aground plane, you must use other strategies, such as placing aground trace next to the signal or using differential instead ofsingle-ended signaling.
Ground bounce also affects signal integrity and relates topower distribution. As with any network that has interconnects,inductance exists in power and ground networks. Asthe I/O signals transition from zero to one or one to zero, transientcurrent flows in the power-distribution network. Manysignals’ switching at once generates large transient currents.Any inductance or resistance in the power- and ground-distributionnetwork converts these transient currents into voltagespikes that appear as noise in other signals or even as a shiftin the ground voltage. Ground planes or multiple ground orpower connections reduce the impedance and therefore theSSO (simultaneous-switching-output) noise. Using lowervoltage swings and protocols that minimize the number of signaltransitions also helps.
Manage signal integrity in your designs
As every RF engineer knows, everything in a circuit canaffect the signal. To manage signal integrity, it is critically importantto first identify the parts of the design that affect signalintegrity. A common approach is to start by creating amodel of your design and its components and interconnects.However, a model typically is less accurate than it needs tobe. You must make measurements of your circuits, comparethem with your model, and adjust the model to make it consistentwith your measurements. Once the model is accurate,you can use the simulator to predict which changes will improvesignal integrity. Pay particular attention to vias, wirebonds, packages, PCB traces, and connectors when consideringcomponents that will affect signal integrity.
The goal of simulation and modeling is to predict the real-worldbehavior of your design. Engineers have traditionally used modern design and simulation environments, such asAgilent’s ADS (Advanced Design System), for microwaveand RF design. As digital speeds approach microwave speeds,engineers have been applying these tools to digital design, especiallyfor evaluating signal integrity. These tools accuratelysimulate high-speed effects, such as distortion, mismatch, andcrosstalk, in your channels.
Making physical measurements is key to assuring the accuracyof your model and validating the final performance ofyour design. At the speeds of next-generation flash design, itis important to analyze the data in both the time domain andthe frequency domain. You can make physical measurements with a time-domain instrument, such as a TDR (time-domainreflectometer), or a frequency-domain instrument, such as aVNA (vector network analyzer).
As the signal travels through the physical structures, theTDR measures and displays impedance. Ideally, the impedancetrace is a flat line, indicating no discontinuities. At the daughtercardvia, you can see a large discontinuity, so you know youmust modify your design to raise its impedance.
Managing interconnect design on PCBs
Active circuitry, packaging, and connectors all influencesignal integrity; PCBs can also influencesignal integrity, often in difficult-to-detect ways. Competing demandsfor high speed and low cost often collideon the PCB. For example, FR4 islow cost and has relatively good performanceat lower data rates. However,when data rates exceed 10 Gbps,problems increase dramatically. Figure5 should help you identify whichelements of your design might be causingproblems and suggests ways to dealwith those problems.The next generation of flash willenable next-generation performance,but next-generation speeds will requiredesigners to pay increased attentionto signal integrity. Understandingwhat can affect signal integrity andhow to model and measure it will helpyou deliver reliable, high-performanceproducts on time and on budget.
This article has also been published on EDN. http://www.edn.com/design/test-and-measurement/4363955/Managing-signal-integrity-in-tomorrow-s-high-speed-flash-memory-system-designs-item-2