ESC 07 Preview: Hardware or software, it's all about the code - Embedded.com

ESC 07 Preview: Hardware or software, it’s all about the code

San Jose, Calif. – A quicksurvey of the papers at next week's Embedded Systems Conference,Silicon Valley, confirms a trend that has been growing for years: theblurring of the distinction between hardware and software development.

It is more than just a matter of more value-added in the softwarethat runs on the hardware than in the hardware itself, as some in theEDA industry, such as PaulMcLellan of Virtutech, hypothesize. 

From a code generation point of view, there is no practicaldifference between hardware and software development, according to someof the papers and classes at the upcoming conference.

Gone are the days of designing integrated circuits with rubyliths.Today, chips are predominantly designed using hardware description languages (HDLs).

That is, the hardware IS software: before being implemented insilicon, most advanced microprocessor, ASIC, FPGA and SoC designs onlyexist in the form of an HDL description such as Verilogor VHDL. That HDL “code” istested, debugged and simulated as vigorously, if not more so, as thesoftware generated for an application.

Even with the fundamental differences between languages for hardwaregeneration and for software generation, the embedded systems developermust keep his/her focus on (1) correct definition and modeling of thesystem, (2) generating the code as quickly and accurately as possible,and (3) employing every technique available to debug and test the codebefore taking the final design steps.

Typifying the two worlds in which embedded developers now live, BobZeidman, president of Zeidman Technologies, has been involved in thedesign of integrated circuits and circuit boards and has writtensoftware for many different types of systems.

A long time speaker at the ESC and a writer for Embedded SystemsDesign on OSes, softwaredevelopment and multicore design, Zeidman is blunt about the issuein a paper he is presenting at ispresenting at ESC Spring (Anintroduction to the Verilog Hardware Description Language [ESC-120]):

If embedded systems developers like their jobs they had better startlearning to use HDLs.

“In order to survive in the future, engineers will need to knowHDLs,” said Zeidman. “ASICs and FPGAs are growing in complexity, whichcan be better handled by HDLs.”

Also presenting¬† at the ESC Silicon Valley is RC Cofer with BenHarding on “AnIntroduction to VHDL (ESC-130). “VHDL has the advantage that it canbe architected and implemented to support simplified designmodification and design reuse,” said Cofer. ” The potential benefits ofVHDL include design self-documentation, design reuse, designportability, tool independence, simplified design update andmaintenance and the benefits of a single language to implement bothhardware functionality and support simulation.”

In many of the papers at the conference on the use of FPGAs inembedded systems, including “Designingthe ultimate system integration platform with 65 nm FPGAs (ESC-302 ),” and “Designingwith Dynamically Reconfigurable FPGAs (ESC-264),” asmuch attention is given to issues relating to the use of HDL toimplement designs as to the underlying hardware details.

But other presenters at the ESC Spring point out that for embeddeddevelopers whose main experience is in programming languages, it maynot be necessary to make the radical shift to HDLs such as Verilog andVHDL. Emerging as competitors are HDL-optimized C-like variants andextensions such as Handel-C,Catapult-C, SystemC, and Mitron-C amongothers.

Unified Modeling Language pioneer andevangelist Stephen J. Mellor, who is presenting “ScalingSystems Design (ESC-103),”¬† proposes the use of executable UMLnotonly as a system definition language for software development, but forVHDL-based hardware development as well.

Two ESC presenters will talk about C-like alternatives that requireeven less re-education than the above C-variants require. One is Impulse-C, fromImpulse Accelerated Technologies, whose CTO, David Pellerin, along withthe company's director of engineering Ralph Bodenner, is presenting “UsingFPGAs as coprocessors for DSP and Image Processing (ESC-263).”

“Tools providing C compilation and optimization for FPGAs can helpto solve these problems by providing a new level of programmingabstraction for FPGA,” said Pellerin. “For applications that involveembedded processors, software-to-hardware tools can abstract away manyof the details of hardware-to-software communication, allowing thesoftware programmer to focus on application partitioning without havingto worry about the low-level hardware. This allows software applicationdevelopers to more quickly experiment with alternativesoftware/hardware implementations.”

Going directly from C to hardware
A direct to C compilation technique that eliminates even themodifications and extensions that such C-variants require is detailedby David Lau and Orion Pritchard of Altera Santa Cruz in “AutomatedGeneration of Hardware Accelerators from Standard C (ESC-330).”

“Methodologies for synthesis of stand-alone hardware modules fromC/C++-based languages have been gaining adoption for embedded systemdesign as an essential means to stay ahead of increasing performance,complexity, and time-to-market demands,” said Lau. “However, using C togenerate stand-alone blocks does not allow for truly seamlessunification of embedded software and hardware development flows.”

Lau and his co-researchers at Altera have developed a C to Hardware(C2H) compiler that starts with standard ANSI/ISO standard C code andgenerates hardware accelerator modules that are tightly coupled with asoft RISC CPU, its tool chain, and its memory system.

This coupling, he said, allows for several significant advancements:(1) a unified development environment with true pushbutton switchingbetween original software and hardware accelerated implementations, (2)direct access to memory from the accelerator module, (3) full supportfor pointersand arrays, and (4) latency-aware pipelining of memory transactions.

“Recursion and floating-point types are the only major exclusionsfromstandard C. Pointers, arrays, structures, and enums, as well as allloop types (including break, continue, and return statements) are fullysupported,” said Lau.

“The C2H Compiler uses an existing commercial system integrationtool to connect the accelerator to the processor and any otherperipherals in thesystem. This gives the accelerator direct access to a memory mapidentical to that of the CPU, allowing seamless support for pointersand arrays when migrating from software to hardware.”

This approach allows the use of the target core CPU's integratedsoftware development environment. “By supporting pointers andun-extended ANSI/ISO C,” said Lau, “the C2H Compiler allows developersto quickly prototype a function in software running on the processor,then switch to a hardware-accelerated implementation with the push of abutton.”

Lau believes that this methodology effectively eliminates theincompatibility between hardware and software design flows, identifiedas one of thecritical problems in the EDA industry. He said eight user test cases oncommon embedded applications show speedup factors of 13-73X achieved inless than a few days.

Regardless of the variant used, said Pellerin, the use of theC-language as the starting point represents a familiar method of methodof abstraction that allows software programmers to access the resourcesof FPGAs for application acceleration without the need to becomehardware designers.

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