ESC 2008 Preview: Dealing with a multi-core design's many facets - Embedded.com

ESC 2008 Preview: Dealing with a multi-core design’s many facets

If you are transitioning from developing applications on traditionalsingle processor designs to ones based on multi-core SoCs or systemswith multiple processors, you have realized that there are a lot ofquestions to be resolved.

For answers to almost any facet of designing with these newarchitectures, speakers at the Embedded Systems Conference Silicon Valleyare prepared to do their best to help you out.

Taking a wide screen look at the issue is David Kalinsky, who willbe presenting “Architectural Design of software formulticore systems (ESC-351/371).”

At first glance, he says, the design of software for multi-coresystems appears to be similar to the design of traditional embeddedmultitasking software. But do not be misled.

“At first glance, the design of software for multi-core systemsappears to be similar to the design of traditional embeddedmultitasking software,” says Kalinsky. “But application software formulti-core systems can often be much larger in scale and much morecomplex than software that has in the past been developed fortraditional single-CPU embedded systems.”

In his class, he will spend a lot of time on methodologicalrecommendations to guide work at this new scale and new level ofcomplexity, with a particular focus of symmetric multi-processing.Despite the familiarity most developers have with SMP, he points out,there are many “gotchas” to deal with, despite the fact that at firstapproximation the guidelines he delves into can be similar to those forthe design of distributed multi-processor systems.

“However, multi-core systems are not simply miniaturized distributedsystems, Says Kalinsky. “Before embarking on the design of software fora multi-core system, some differences between multi-core anddistributed systems must be understood, and then taken into accountwhen architecting software that is destined to run on multi-core SOCs(Systems-On-a-Chip).

“Many of the design assumptions that have been the firm foundationof embedded systems multitasking software design for the past 20-30years, are no longer valid when designing software for multi-coreSOCs.”

Performance modeling and analysis
According to Ali Poursepanj, who is presenting “Performance modeling and analysis ofmulticore-SoC systems (ESC-266), the architecture and designof such systems has become challenging due not only to their complexitybut also to the contradictory demands for higher performance, but atreasonable cost and reduced power.

In his class, he will go into detail on some of the performanceanalysis techniques available for multicore SoC products and highlightsome of their respective challenges. There are analytical, transactionlevel, and cycle accurate models that are used to study the performanceof the SoC systems, he points out with benefits and features that haveto be carefully balanced one against the other.

“The analytical models are used at the early stage of the designprocess; the transaction models are developed and used after initialmodeling using analytical tools,” says Poursepanj. “The cycle-accuratemodels are developed and used to accurately project the SoC systemperformance and fine tune the microarchitecture.. The hybrid modelshave a functional model piece, that can boot the operation systems andrun the real applications of interest, and a cycle-accurate piece thatis used for performance analysis.”

There are a number of challenges in multi-core SoC systemperformance modeling, he warns, including the availability of targetapplication descriptions, representation of application workloadmodels, transition of transaction level models to a cycle accuratemodel, speed of cycle accurate models, availability of models in atimely manner during the design cycle, cost of hybrid model developmentand re-usability of performance models in verification environments.

“In spite of the complexity and cost of performance modeling formulti-core SoC systems though, the pay off is significant,” saysPoursepanj. When the product's performance is right the first time, inadvance of the silicon everyone wins.”

Planning for the future
If you are planning in your next multi-core SoC design to use theshared bus architecture that served you so well in earlier uniprocessorsystems and sort of ok in your first run at multiprocessing, don't. Notif you are planning to scale it up for future iterations of yourproduct.

That is the message of Sanjay R. Deshpande, who is teaching “Interconnections for multi-core systems(ESC-531),” at the 2008 Embedded Systems Conference SiliconValley in mid-April.

“Using a single bus to interconnect all of a system's components cansimplify design,” he says, “but it seriously impairs overallperformance if the system has a large number of cores and otherdevices.

“As core counts rise, shared bus architectures common in somemulti-core approaches are actually impeding the fulfillment ofultra-high performance levels due to fundamental bottleneck and latencyissues.

Performance and scalability can greatly depend on the robustness ofsystem's interconnect and its ability to optimally manage access to andfrom each resource. Therefore, he says, it is critical to leverage ascalable interconnection scheme that performs as well for dual coreprocessors as it does for devices featuring 32 cores.

A bus topology, he points out, is not very scalable. “The larger thesystem scales, the more entities are connected to the bus. The wiresare longer and the fan-out is higher, resulting in longer propagationtimes and lower bus frequency. In addition, more entities requestservice from the bus, lengthening queuing delays, which increaseslatencies and lowers throughput.”

The best alternative, says Deshpande, are one of the severalfabric-based multi-core interconnect schemes that have emerged andwhich are the focus of his class. Not only can such topologies bedesigned specifically to remove performance barriers, he says, hey canbe more easily scaled to keep up with demands of the marketplace.

Using SMP Multi-cores – and theirOSes
At the Embedded Systems Conference Silicon Valley, Michael Anderson,CTO and chief scientist at The PTR Group does double duty, coveringmulti-core design from both the hardware and the OS sides.

In “Understanding and Using SMP Multi-coreProcessors (ESC310/330),” he presents the case for symmetricmultiprocessing (SMP) as the basic architectural building block formost of the current generation of multicore designs.

” In spite of the hype associated with homegenous, multicoreprocessors,” says Anderson, ” They are really simply SMP systems inminiature. And SMP has been with us for a long time already, so it's avery stable and mature technology. Even if you do nothing but runsingle threaded applications, you will see some performance speed upsimply because you can run more than one application at a time.

“However, if you really want to take advantage of everything thatSMP can offer, then you need to 'bite the bullet' and learn how towrite multithreaded applications. It sounds intimidating at first, butthere are a lot of good examples available on the web, especially whenusing the POSIX pthreads API.”

Operating systems on multicore designs are another matter. AndAnderson devotes and entire class on “Understanding Multicore Embedded OperatingIssues (ESC-432),” to the subject.

“As MCPs become more prevalent in embedded systems operating systemswill need to adapt to support them,” he says. ” Interprocessorcoordination, affinity and mutual exclusion among other issues willneed to be in the forefront of the embedded designer's thoughts as theychoose or build the OS with the correct characteristics for theirapplication.”

Learning by example – and case study
If you learn best by getting you hands around the actual hardware andyour mind around the software issues, the best way to get a handle onmulti-core is in “Case studies in software optimization forMulticore SMP (ESC-471), ” reprised by Max Domeika, seniorstaff engineer in the Developer Products Division at Intel Corp.

In addition to providing a wealth of case studies and examples toillustrate the software considerations for shared- memory multicoredesigns, he focuses his class on the Threading Development Cycle (TDC).

In it he will discuss includes analysis, design, debugging, andtuning for multithreading as well as some common challenges to overcomewhen threading such as data races and cache conflicts as well as toolssupport and practical techniques available to assist with stability andperformance. Case studies involving a data parallel application and afunctional parallel application help reinforce the discussion.

Ckick  here to  register for the  Embedded  Systems  Conference Silicon Valley.

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