ESL tool tames one tough task: On-chip register design -

ESL tool tames one tough task: On-chip register design

Palo Alto, Calif.—If you design complex digital chips, you'll want to know about Blueprint, an electronic system level (ESL) tool from Denali Software Inc. that automatically generates and manages the vast number of on-chip control registers that you no doubt find yourself juggling.

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Blueprint aims to eliminate the tedious and error-prone task of addressing all the elements of register management, including describing and generating control register logic. Working from a register description language, Blueprint creates outputs for hardware design, software development, verification, and documentation. In this way, it lets design, verification, and software teams work from consistent, synchronized views of a chip's design.

For example, Blueprint produces Verilog, SystemVerilog, or VHDL for control registers as well as Open Verification assertions that ensure that registers and control logic operate correctly. For functional verification, it creates output models of registers for use in C/C++, SystemC, OpenVERA, “e,” Verilog, and System Verilog.

For software, Blueprint generates headers, classes with access methods, and a complete hardware abstraction layer. Blueprint also generates test cases for pre- and postsilion validation of logic. And for documentation, it issues files compatible with user templates for Framemaker, Microsoft Word, HTML, XML, and SGML.

Blueprint's well-defined, object-oriented architecture is extensible, letting you create new and customized code generators for specific applications.

Blueprint is available now and costs $500,000 annually for an enterprise site license.

Denali Software Inc. , 1-650-461-7200,

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