Estimating power in embedded systems using an advanced DSP -

Estimating power in embedded systems using an advanced DSP

Multiple variables affect thepowerrequirements of embedded systemsthat use an advanced processor. In addition to the fabrication process,the ambient temperature, core and system frequencies, supply voltages,pin capacitances, power modes used, application code, and peripheralutilization all contribute to the average total power that may bedissipated.

Systems can operate in multiple states that range in processingintensity. Because of this, when it is necessary to calculate a trueaverage power dissipation, it is best to collect a statistical analysisto determine what percentage of the time the processor spends in eachof the defined states. For example, consider an application with thefollowing profile:

STATE1= 20% of application
STATE2 = 10% of application
STATE3 = 70% of application

In this case, the total average power (P TOT )is summarized asfollows:

P TOT = (0.2*PSTATE1) + (0.1*PSTATE2)+ (0.7*PSTATE3)

While average power estimates are useful in terms of expected powerdissipation within a system, designs must support the worstconditionsunder which the application can be run.

This article describes a methodology for estimating total averagepower consumption, using the ADSP-BF533Blackfinfamily ofprocessorsas an example.

Average Power Consumption
Total average power consumption (P DDTOT ) is the sum of the averagepower dissipated in each of the three power domains in a Blackfinapplication: internal supply (V DDINT ), external supply (V DDEXT ),and, optionally, Real-Time Clock supply (V DDRTC ).There aredifferent supply voltages because the core does not operate at the samevoltage as the I/O. The core operates within the range of 0.8-1.32Vwith a nominal rating of 1.2V (V DDINT ).

The I/O circuitry supports a range of 2.25-3.6V with a nominalrating of 2.5V or 3.3V (V DDEXT ), depending on the system. Insome products, 1.8V operations are supported. The Real-Time Clock canbe powered by either the I/O supply or a battery.

The Hibernate power mode on the ADSP-BF533 processor allows power tobe removed from the core and, optionally, removed from the I/O. Toallow a Real-Time Clock event to restore power to the core afterexiting Hibernate mode, the Real-Time Clock must remain powered by aseparate supply. A third power domain (V DDRTC ) satisfiesthis need.

Since power is defined as the product of the supply voltage and thecurrent drawn, the power domains are described by the equations:


For the purposes of this discussion, current and power values aretreated as average values and voltages are assumed to be constant. Thetotal average power dissipated by the processor is the sum of threecomponents:


Average Internal Power Consumption
There are a few things to consider when estimating the average internalpower dissipation of a processor. The first consideration is the factthat internal power is composed of two components, one static and onedynamic.

The static component, as the name implies, is independent oftransistor switching frequency. It is a reflection of “leakage”current, which is a phenomenon that causes transistors to dissipatepower even when they are not switching. Leakage is a factor inhigh-performance CMOS circuit design andis a function of both thesupply voltage and the ambient operating temperature at which the partis expected to run. Leakage current increases as temperature and/orvoltage increases.

The dynamic power component is largely independent of temperatureand is a function of supply voltage and switching frequency. The fasterthe transistors can switch, the more that voltage swings occur. Thehigher the supply voltage, the larger the voltage swing between the onand off transistor states. Thus, the dynamic component will increasewith voltage and/or frequency.

Finally, the actual power numbers can fluctuate within a definedrange based on the processor fabrication process at the transistorgeometries required for such high speeds. This is largely due to thesemiconductor doping process (i.e., ion implantation), which does notresult in uniform connectivity among the transistors, yielding slightvariations of the die in any given wafer of silicon.

Other physical phenomena related to the fabrication process alsocontribute to this non-uniformity. These physical differences causesome die to conduct faster than others, which results in threeprocess-related groupings.

Estimating Average Static Power
The static component for average internal power is a result of theleakage current that occurs even when the transistors are not changingstate. When the clocks (core and system) are off and voltage is appliedto the core and L1 memory, Blackfin processors are in “Deep Sleep “mode.

The static current component, I DDDEEPSLEE P is ameasurement that indicates the static current component contributing tothe internal static power consumption, (P DDINT_ST ):


Another important factor relative to leakage current is ambienttemperature. Static power consumption increases exponentially withambient temperature, as detailed by the equation:

P DDINT_ST@T = P DDINT_ST@T0 * e (0.015 *(T ” T0))

where P DDINT_ST@T0 is the power dissipateddue to leakagecurrent at the known temperature (T 0 ) and P DDINT_ST@T is the number at the target temperature (T ).

In summary, these methods can be applied for the acceptable ambienttemperature range once a baseline “Deep Sleep” mode current measurementis obtained from the part in question at the operating voltage ofchoice.

Estimating Average Dynamic Power
The dynamic component of average internal power is a function of theoperating frequency and the supplied voltage. Now let's look at theprocess of extrapolating measurements by virtue of frequency andvoltage scaling.

Once the current consumption at a frequency is known, the expectedcurrent draw can be calculated at any frequency:

I DDINT@F = I DDINT@F0 + [(F ” F 0 ) *Ratio

where F is the targetfrequency, F 0 i sthe knownfrequency, and Ratio is thechange in current draw per change infrequency.

A common question regarding frequency scaling is “Why is the currentdraw at 600MHz not equal to 1.5 times the value obtained at 400MHz?”.

The basis for this question is understandable because the ratio from400MHz to 600MHz is 1.5. However, the answer is based on thefundamental understanding that the static power component is notaffected by a change in frequency. The measured value IDD contains both the static and dynamic components:


where I DDDEEPSLEEP is the leakage, which remainsconstantacross the frequency domain, and I DDFAST_DYN is the dynamiccomponent, which is affected by changes in frequency. Since the intentis to apply the dynamic power ratio to the current draw measurement,the static component must be removed prior to performing thisoperation:


Because the frequency is being increased by a factor of 50%, thedynamic ratio can be applied:

IDD_DYN600 = 1.5 * IDD_DYN400

At this point, the static component can be added back in, yieldinga total estimated current drawn:


The ratio of dynamic power consumption from one applied voltage toanother is directly proportional to the square of the voltage ratioitself, or:


The current component is easily extracted by dividing this value bythe supply voltage:


Now the static component at 1.32V can be added:


These extrapolation methods can be taken a step further by applyingboth the frequency and voltage scales with one equation. Since thefrequency ratio is linear, it can be factored into the equation usedfor voltage scaling:

P DDDYN@V = P DDDYN@V0 * (V/V0) 2 *(F/F 0 )

where V 0 is the reference voltage, V is the targetvoltage, F 0 isthe reference frequency, and F is the targetfrequency. For example, the current values in Table 1, below at F0 =400MHzand V0 =1.2V are known and the wish is to obtain theestimated measurements at F=600MHz and V=1.32V.

Table1. Average IDDINT on Faster Part (1.2V)

Again, the first step is to remove the static component. Second, theknown values are substituted into the equation:

P DDDYN@V = P DDDYN@V0 * (V/V 0 ) 2 * (F/F 0 )

P DDHIGH_DYN = P DDFAST_DYN * (1.32/1.2) 2 * (600/400)

The current component is easily extracted by dividing this value bythe supply voltage:


Now the static component at 1.32V can be added:


In summary, there are many methods available to estimate internalpower consumption based on the values presented in the data sheet or onvalues obtained under nominal conditions when considering worst-caseoperating conditions.

Average External Power Consumption
Average external power dissipation is the average power dissipated inthe V DDEXT power domain. The number ofcomponents thatcontribute to the overall external power value is the number of enabledperipherals in a given system. Each unique group of peripheral pinscontributes to a piece of the overall external power based upon severalparameters:

* Number of output pins (O )
* Number of pins toggling each clockcycle (TR)
* Frequency at which the peripheralruns (f )
* Utilization factor – percentage of time that the peripheral is on (U )

* Load capacitance (C )
* Voltage swing (V DDEXT )

The equation used to derive each component's contribution to thetotal external power is:

P DDEXT = (VDDEXT ) 2 * C * f/2 * (O*TR) * U

The worst external pin power scenario is when the load capacitorcontinuously charges and discharges, requiring the pin to togglecontinuously. Since the state of the pin can change only once percycle, the maximum toggling frequency is f/2. In terms of supply power,the worst-case V DDEXT value is 3.65V. The example belowcontains data for a realistic example of a PPI application, which runsseveral peripherals simultaneously. Actual results may vary, but again,the intent is to help designers size the power supplies.

In the example, the total average external power consumption isestimated to be about 170 milliwatts (mW). This number was obtainedwith the parameters listed and by applying the P DDEXT equation givenabove. Notice that the recommended load capacitance of 30 picofarads(pF) when the VDDEXT is 3.65V was used in this calculation.

The chosen operating frequencies are reasonable for each of theperipherals, including the maximum allowed SDRAM frequency of 133MHz.This model assumes that each output pin changes state every clockcycle, which is a worst-case model, except in the case of the SDRAM(because the number of output pins transitioning each clock cycle willbe less than the maximum number of output pins).

Rather than estimating average external power dissipated in eachperipheral, the estimate applies to each individual output pin, basedon the pin's load capacitance and average toggling frequency. Thevoltage swing is uniform across all output pins within the V DDEXT supply domain, so it is multiplied by the summation of the dynamiccharge changes on each output.

Using the PPI data, nine output pins change every cycle at anaverage frequency of 27MHz. Since toggling between on-to-off andoff-to-on requires two cycles, F AVG is half the PPI clock (13.5MHz).Since each pin changes at the same rate and the pin capacitance is,presumably, the same, the summation is simply nine times the value ofany one PPI pin:

P EXT_AVG = V DDEXT2 * 9 pins * (F AVG * C L ) = (3.65) 2 * 9* 13.5e6 * 30e-12 = 13.3225 *0.003645 = 0.048561W = 48.561mW

As can be seen, the value derived using this equation isthesame as the value estimated in Table2 below . This model obtains thesame estimate on a per-pin basis rather than a per-peripheral basis.Finally, a board designer must also be mindful of power supplyefficiency when sizing the V DDEXT supply.

Table2. Sample Calculation For Total Average External Power

Real-Time Clock (RTC) Power Consumption
The final source of total power consumption comes from the optionalthird power domain, the Real-Time Clock power domain (V DDRTC ),which is a specified value.

The RTC can be powered between 2.25Vand 3.6V.


Knowing this value alsohelps inselecting a batteryas a potential power source for the RTC. The RTC can be used to takethe ADSP-BF533 processor out of any of the low-power operating modes.Having a battery supply the V DDRTC domain allows the removalof the V DDINT and V DDEXT supplies, thussignificantly reducing total average power consumption.

Additional information isavailable fromwww/

JoeBeauchemin is aSenior Applications Engineer atAnalogDevices. He can be reached at
[1] ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Embedded ProcessorPreliminary Data Sheet. Rev. PrC, January 2004. Analog Devices
[2] External PowerSpreadsheet. Associated file with Estimating Powerfor ADSP-BF533 Blackfin Processors (EE-229) February 2004. AnalogDevices.
[3] SwitchingRegulator Design Considerations for ADSP-BF533 BlackfinProcessors (EE-228). Rev 1

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