Evatronix's HSIC compatible PHY IP saves power, reduces silicon area - Embedded.com

Evatronix’s HSIC compatible PHY IP saves power, reduces silicon area

Evatronix SA has introduced a High Speed Inter-Chip (HSIC) compatible PHY IP for significant power and area savings in USB 2.0 chip-to-chip connections. Implementation of the HSIC technology enables setting up a direct connection on a PCB board between a USB host chip and other on-board USB devices.

The HSIC standard features much less power consumption thanks to elimination of requirements to support long external USB cables while remaining USB protocol-compliant and thus USB software compatible. The possibility for straightforward use of all the available USB software gives HSIC an advantage over other inter-chip connection standards such as I2C.

Through the implementation of a 240MHz DDR interface, the HSIC standard provides full support for the 480Mbps data transfer of the USB protocol. By elimination of 3.3 and 5V signaling, the HSIC interface enables significant silicon area and power savings in comparison to standard cable USB 2.0 PHYs.

The Evatronix USBHSIC-PHY logic macro is available now on the LFoundry 150nm process with the possibility to port it to any technology node from 65 to 180nm.

For more information visit www.evatronix-ip.com.

Toni McConnel can be reached at toni@techrite-associates.com.

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