In part 1of this series, we discussed the major differences between NAND and NOR Flash. In part 2, we focused on the electrical interface of different types of NOR Flash devices and how this impacts device selection and design. Part 3 covered the electrical interface of different types of NAND Flash devices and how this impacts device selection and design. Part 4 explored the different types of NAND Flash based on their internal architecture and the way data is stored in their memory cells.
In this part we will focus on the different errors in NAND Flash. As explained in part one, NAND Flash is more prone to errors than NOR Flash owing to its structure. The errors in NAND Flash can be classified into two major categories: permanent (non-correctable) errors and temporary (correctable) errors. Memory wear is the permanent error in NAND Flash. Temporary errors in NAND Flash are Program Disturb, Read Disturb, Over-programming and Retention errors. A detailed explanation of each type of errors follows.
Memory wear, also known as endurance error, is a permanent error in NAND Flash. As explained in the part 4, memory wear is caused by program and erase operations. Every time a cell is programmed or erased, a few electrons get stuck in the oxide layer, thereby wearing out the oxide layer. Once the cell reaches a point where the controller can no longer reliability distinguish between programmed and erased states, the cell is considered as bad or worn out. The block with the worn out cell is now considered as a bad block and is not used any longer.
Read Disturb Error
As the name indicates, a read disturb error is caused by read operations. Let’s consider the read operation in detail.
To read a memory cell, the charge stored in the floating gate needs to be identified by measuring the threshold voltage of the cell. A reference voltage is applied at the gate terminal of the required cell and the voltage at which the cell starts conducting is measured to identify the threshold voltage. Since the memory cells are connected as strings in NAND Flash, all other cells in the string need to be turned on prior to reading the required cell. A readout voltage (VREAD ), higher than the maximum threshold voltage of the memory cells, is applied to the gate terminal of all other cells in the string to turn them on or unselect the cells. In NAND Flash, the gate terminals of multiple memory cells in different strings are connected together as a page. To unselect a cell in the string, the entire page need to be unselected, which means the readout voltage needs to be applied to the gate terminals of all the cells in a page.
Even though the readout voltage is much smaller compared to program or erase voltages, this can still cause a slight shift in the threshold voltage of the cells. These small shifts in threshold voltage accumulate over read cycles, eventually changing the state of the cell. This unintentional shift in the threshold voltage of a cell due to read operation is known as read disturb error. More details on read disturb errors are available in Read Disturb Errors and How to Recover From Them. Note that read disturb errors affect only the cells in unselected pages in the same block being read. As this is a temporary error, the error can be resolved by copying the block to another block, then erasing the errored block to make it available again.
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Figure 1: A read disturb error affects the cells in unselected pages in the same block being read.
Program Disturb Error
A program disturb error, caused by cell-to-cell programming interference, is another correctable error in NAND Flash. As explained previously, a high voltage is applied across the memory cell for program and erase operations. Due to parasitic capacitive coupling, the adjacent cells also receive an elevated voltage stress that can alter the threshold level of these neighboring cells. This unintentional shift in threshold level due to program or erase operations in known as a program disturb error.
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Figure 2: A program disturb error occurs from an unintentional shift in the threshold level due to program or erase operations.
A program disturb error affects cells in both selected and unselected pages, but only in the block being programmed. The parasitic capacitive coupling between adjacent cells increases with shrinking lithographic node, the same reason the Raw Bit Error Rate (RBER) increases for smaller lithographic nodes. To recover from this error, the block needs to be erased after copying its contents to another block.
Over-programming is another correctable error in NAND Flash. While programming, the threshold voltage of some cells can go too high. As explained in the previous sections, memory cells need to be turned on or unselected for read and program operations. Cells with a very high threshold voltage will not turn on as expected when readout voltage is applied. This can result in incorrect read and program operations for other pages in the string. This is known as an over-programming error.
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Figure 3: An over-programming error occurs when the threshold voltage for a cell goes too high, which causes the cell not to turn or be selected during read and program operations.
Over-programming errors are often caused by memory cells that hold a higher initial charge on the floating gate due to an improper erase operation. They also occur when memory cells are nearing a worn out state. To recover from this error, the block need to be erased after copying the contents to another block.
The data stored in Flash memories tend to get corrupted over time. This is known as a data retention error. Retention errors are caused by loss of charge stored in the floating gate. Even though the gate oxide is an insulating layer, electrons stored in the floating gate still leak through it from time to time. With longer durations, the loss of charge accumulates, eventually changing the programmed state of the cell and causing a data error. To recover from this error, the block need to be erased after copying the contents to another block.
Retention errors can happen to any cell in any block of the Flash memory. Due to wear of the oxide layer, memory cells with more program erase cycles are more likely to experience retention errors. Temperature is another factor which contributes to retention error; the higher the temperature, the greater the chance for a retention error. In MLC, TLC, and QLC memories that store more bits in each memory cell, the cells with more programmed electrons (closer to binary 0) are more prone to leakage of charge. Retention errors depend on many aspects of the Flash manufacturing technology such as lithographic node, oxide thickness, and so on. Data retention is a key parameter in all Flash datasheets.
Avinash Aravindan is a Staff Systems Engineer at Cypress Semiconductor. His responsibilities include defining technical requirements and designing PSoC based development kits, system design, technical review for system designs and technical writing. He has 8+ years of industry experience. He earned his Master’s Degree on Master of Science in Research on Information and Communication Technologies (MERIT) from Universitat Politècnica de Catalunya, Barcelona, Spain and B.Tech from Cochin University of Science and Technology, Cochin, India. His interests include embedded systems, high-speed system design, mixed signal system design and statistical signal processing.