In part 1of this series, we discussed the major differences between NAND and NOR Flash. In part 2, we focused on the electrical interface of different types of NOR Flash devices and how this impacts device selection and design. Part 3 covered the electrical interface of different types of NAND Flash devices and how this impacts device selection and design. Now we will focus on the different types of NAND Flash based on their internal architecture or the way data is stored in the memory cells.
Since the cost of Flash depends on its die area, Flash would be more cost effective if more data can be stored in the same area. There are three main types of NAND Flash: Single Level Cell (SLC), Multi Level Cell (MLC) and Triple Level Cell (TLC). As the name suggests, a TLC Flash stores more data in an equivalent area than an MLC, which in turn stores more data than SLC. Another type of NAND Flash is known as 3D NAND or V-NAND (Vertical-NAND). This type of Flash achieves a greater density by stacking multiple layers of memory cells vertically on the same wafer.
Floating Gate Transistor
In the first part of this series, I mentioned that Flash memories store information in memory cells made of floating gate transistors. To better understand the different types of NAND Flash memories, let’s look at the structure, workings, and limitations of floating gate transistors.
A floating gate transistor or floating gate MOSFET (FGMOS) is quite similar to a regular MOSFET except it has an additional electrically insulated floating gate between the gate and the channel.
Figure 1: A floating gate transistor or floating gate MOSFET (FGMOS) is similar to a regular MOSFET except it has an additional electrically insulated floating gate between the gate and the channel.
Since the floating gate is electrically isolated, any electron reaching the gate will get trapped there even after the voltage is removed. This provides the non-volatile property of the memory. Unlike a regular MOSFET, which has a fixed threshold voltage, the threshold voltage of an FGMOS will depend on the amount of charge stored in the floating gate. The more charge, the higher the threshold voltage. Similar to a regular MOSFET, when the voltage applied to the control gate is more than the threshold voltage, the FGMOS will start conducting. The information stored in the FGMOS is thus identified by measuring its threshold voltage and comparing it against a fixed voltage level. This is termed as a read operation in Flash memory.
Electrons can be placed in the floating gate using two methods: Fowler-Nordheim tunneling or hot-carrier injection. For Fowler-Nordheim tunneling, a strong electric field is applied between the negatively charged source and the positively charged control gate. This causes electrons from the source to tunnel through the thin oxide layer and reach the floating gate. The voltage required for tunneling depends on the thickness of the tunnel oxide layer. With hot-carrier injection, a high current is passed through the channel, giving sufficient energy to the electrons to tunnel through the oxide layer and reach the floating gate.
The electrons can be removed from the floating gate using Fowler-Nordheim tunneling by applying a strong negative voltage on the control gate and strong positive voltage on the source and drain terminals. This will cause the trapped electrons to tunnel back to the channel though the thin oxide layer. In Flash memory, placing the electrons in the floating gate is considered a program/write operation, and removing the electrons is considered an erase operation.
The tunneling process has a major disadvantage: It gradually damages the oxide layer. This is termed as wear in Flash memory. Every time the cell is programmed or erased, a few electrons get stuck in the oxide layer, thereby wearing out the oxide layer. Once the oxide layer reaches the point where it can no longer be reliability distinguished between a programmed and erased state, the cell is considered as bad or worn out. As read operations do not require tunneling, they do not wear the cell out. This is why the life of Flash memories is expressed as the number of program/erase (P/E) cycles it can support. Understanding Typical and Maximum Program/Erase Performance provides an explanation on how the typical and maximum values for program and erase performance are derived.
Single Level Cell (SLC) NAND Flash
In SLC Flash, each memory cell stores only one bit of information: either logic 0 or logic 1. The threshold voltage of the cell is compared against a single voltage level and the bit is considered as logic 0 if the voltage is above the level and as logic 1 if below.
Figure 2: The voltage in an SLC Flash cell is compared against a threshold voltage to determine if it is a logic 0 (above the threshold) or logic 1 (below the threshold).
Since there are only two levels, the voltage margin between the two levels can be quite high. This makes it is easier and faster to read the cell. The Raw Bit Error Rate (RBER) is also low due to the lower impact of any leakage or disturbances during read operations owing to the larger voltage margin. A low RBER also reduces the number of ECC bits required for a given block of data.
Another advantage of the large voltage margin is that the effect of wear is comparatively less as minor leakage of charges will have relatively lower impact. The wider distribution for each logic level helps the cells to be programmed or erased with lower voltages, which further increases the endurance of the cell, in turn increasing the number of lifetime P/E cycles.
One disadvantage is the higher cost per cell compared to other types of Flash that store more data in the same die area. SLC Flash is often used in applications that are not cost sensitive and require high reliability and durability, such as industrial and enterprise applications with a large number of required P/E cycles.
Multi Level Cell (MLC) NAND Flash
In MLC Flash, each memory cell stores two bits of information, i.e., 00, 01, 10 and 11. The threshold voltage is compared against three levels in this case (total 4 voltage bands).
Figure 3: The voltage in an MLC Flash cell is compared against three threshold voltages to determine its logical two-bit value.
With more levels to compare, the read operation needs to be more precise, making reads slower compared to SLC Flash. The Raw Bit Error Rate (RBER) is also comparatively higher owing to the lower voltage margin, and more ECC bits are needed for a given block of data. The effect of wear is more significant now as any leakage of charges will have a larger relative impact compared to SLC Flash, in turn reducing the number of lifetime P/E cycles.
The program operation is also much slower as programming need to be done carefully to store the charge within the tight window required for each logic level. The primary advantage is lower cost per bit, which is 2-4x lower than SLC Flash. MLC Flash is often used in more cost sensitive applications such as consumer electronics or gaming systems where performance, reliability, and durability are not as critical and the number of lifetime P/E cycles required is comparatively low. SLC Versus MLC NAND Flash Memory offers a more detailed comparison of SLC and MLC Flash memories.
Enterprise Multi Level Cell (eMLC) NAND Flash
The low reliability and durability of MLC Flash makes them undesirable for enterprise applications while low cost is a driving consideration. To bring in the advantages of lower cost, Flash manufacturers have created an optimized grade of MLC Flash with higher reliability and durability known as eMLC. The density of data is often reduced in eMLC, which provides better voltage margins to improve reliability. Slower erase and program cycles are generally used to reduce the effect of wear and improve durability. There are many other techniques to improve the reliability and durability in eMLC, which varies from one manufacturer to another.
Triple Level Cell (TLC) NAND Flash
In TLC Flash, each memory cell stores 3 bits of information. The threshold voltage is now compared against seven levels (total 8 voltage bands).
Figure 4: The voltage in a TLC Flash cell is compared against seven threshold voltages to determine its logical three-bit value.
With much more levels to compare, read operations need to be highly precise and are slow compared to SLC Flash. The Raw Bit Error Rate (RBER) is also high, increasing the need for even more ECC bits for a given block of data. The effect of wear is amplified as well, drastically reducing the number of lifetime P/E cycles. The program operation is slower too as the voltage needs to be precise to store the charge within the more stringent window required for each logic level.
The key advantage is the lowest cost per bit, which is much lower compared to SLC or MLC Flash. TLC Flash is used in highly cost sensitive applications with less need for a high lifetime P/E cycle, such as consumer applications.
Comparison of SLC, MLC, eMLC and TLC
A comparison of the major parameters of the different types of Flash, assuming similar lithographic processes, is given in Table 1. The values are only indicative to compare performance and may not be accurate in terms of a specific memory product.
|Bits per cell||1||2||2||3|
|Cost per bit||Highest||Moderate||Moderate||Lowest|
|Data Retention||10 years||1 year||1 year||1 year|
|Read||25 µs||50 to 60 µs||50 to 60 µs||105 µs|
|Program||200 µs||1.1ms to 1.3ms||2ms||4.65 ms|
|Erase||2ms||3 to 4ms||6ms||10ms|
|ECC (per 512 bytes)*||1-bit to 12-bit||4-bit to 40-bit||4-bit to 40-bit||More than 60-bits|
Table 1: A comparison of the major parameters of each of the different types of Flash.
* The number of ECC bits depends on the technology node; smaller technology nodes require more ECC bits.
3D NAND Flash
All the different Flash memories discussed above are two-dimensional, meaning the memory cells are arranged only in the X-Y plane of the wafer. With 2D Flash technology, the only way to achieve greater density in the same wafer is to shrink the lithographic process. The downside of this is that errors in NAND Flash are more frequent with smaller lithographic nodes. In addition, there is a limit in the minimum lithographic node that can be used.
To increase memory density, manufacturers have developed 3D NAND or V-NAND (vertical NAND) technology which stacks memory cells in the Z plane on the same wafer. Building up in this way helps achieve great bit density for the same die area. In 3D NAND Flash, memory cells are connected as vertical strings as opposed to horizontal strings in 2D NAND.
The first 3D Flash products had 24 layers. With the advance of this technology, 32-, 48-, 64-, and even 96-layer 3D Flash memories have been fabricated. The advantage of 3D Flash is a significantly higher number of memory cells in the same area. This also enables manufacturers to use larger lithographic processes to fabricate more reliable Flash.
Another major technology shift seen in 3D Flash is the use of charge trap Flash instead of floating gate transistor. A charge trap is similar to FGMOS in structure except that the floating gate is replaced with a silicon nitride film. Note that charge traps were not widely used in the market due to difficulties in manufacturing on a large scale. Charge trap technology has been adopted for use in 3D Flash due to difficulties in fabricating vertical strings of floating gate transistors and the other inherent advantages of charge trap.
There are many advantages with charge trap-based memory over FGMOS. Charge trap-based memory can be programmed and erased at lower voltages, thus improving durability. As the trapping layer (nitride) is an insulating layer, charge does not leak, thereby increasing reliability. Since charge does not flow from one side of the charge trap to the other, more than one bit can be stored on the same trap layer. Cypress (former Spansion) has effectively used this capability in NOR Flash memories, termed as MirrorBit technology, to store two bits of data in a single memory cell similar to MLC Flash.
All the major Flash manufacturers are aggressively working on different methods to reduce the cost per bit of Flash while still creating products that are useful in various applications. Active research is going on to increase the number of vertical layers in 3D NAND Flash. While 15nm seems to be the smallest successful node for NAND Flash today, the shrinking of lithographic nodes for Flash is still being pursued. Combining MLC and TLC technologies with 3D NAND Flash is also actively being explored, and many manufacturers have already seen success. With the advent of newer technologies, we may soon see memory cells that can store a byte of data and vertical layers reaching 256 layers and even beyond.
In part 5, we will focus on the different errors associated with NAND flash.
Avinash Aravindan is a Staff Systems Engineer at Cypress Semiconductor. His responsibilities include defining technical requirements and designing PSoC based development kits, system design, technical review for system designs and technical writing. He has 8+ years of industry experience. He earned his Master’s Degree on Master of Science in Research on Information and Communication Technologies (MERIT) from Universitat Politècnica de Catalunya, Barcelona, Spain and B.Tech from Cochin University of Science and Technology, Cochin, India. His interests include embedded systems, high-speed system design, mixed signal system design and statistical signal processing.