Today’s flash-based gate arrays are more than just a collection of configurable gates. The arrays now contain many other dedicated functions that reduce system design time, improve logic utilization, lower system cost and power, and deliver better performance than equivalent functions implemented in just the configurable logic. Predesigned function blocks conserve the basic logic resources of the FPGAs and, in some cases, implement functions not possible to build using the logic fabric in the FPGA.
In many applications SRAM-based FPGAs can offer similar features and functions. However, since the FPGAs use SRAM cells to hold the configuration patterns, when power disappears so does the configuration pattern. When power is restored, the system must reload the configuration pattern, typically through a serial interface, and that can take tens to hundreds of milliseconds.
In contrast, in flash-based FPGAs non-volatile memory cells hold the configuration pattern right on the chip, and even if power is removed the contents of the flash cells stay intact. Thus when the system restarts, the FPGAs power up in microseconds, saving time and allowing the system to recover quickly from a power failure or a restart.
In the past, flash-based FPGAs trailed behind the SRAM-based devices in density, performance, and on-chip features such as processor cores, high-speed I/O channels, and other functions requiring high density. This trailing edge was mainly due to the challenge of shrinking the flash memory cell, which typically required larger dimensions than the rest of the logic on the chip. The larger dimensions, in turn, resulted in slower performance and the inability to integrate high-performance processor cores and other functions on the FPGA.
However, advances in process technology now allow the FPGA designers to shrink the flash configuration cells and integrate them into advanced logic processes, enabling high-performance flash-based FPGAs to deliver features and functions comparable to or even better than what SRAM-based FPGAs can deliver, and often at a lower system cost. Additionally, since an external configuration memory is not needed, the flash-based arrays have a reduced system footprint and consume less power.
Flash technology has transitioned from a specialty process to the mainstream, allowing flash-based FPGAs to compete in cost-sensitive markets while delivering logic densities of over 150k logic (Figure 1 ). The integrated functionality of flash FPGAs also delivers system-level solutions which help reduce system complexity, lower system power and reduce overall system cost.
Figure 1: For FPGAs with up to 150k logic elements, there are many available market opportunities that range from about $300 Million for the Defense and Security markets to $500 Million for the combined wireline and wireless markets.
Figure 2 provides a short comparison of the features integrated into flash-based FPGAs vs comparable density SRAM-based FPGAs.
While there is much in common between flash-based FPGAs and comparable density SRAM-based FPGAs, there are also many significant feature differences aside from the flash or SRAM configurability. Chief among these differences are the quantity of I/O pins, the number of SERDES channels, and the inclusion of a high-performance memory subsystem as well as embedded security functions including AES256 or SHA256 encryption/decryption capabilities.
For the mid-range densities, designers have a wide choice of features, I/O pins, and package options to meet just about any system requirement. However, the various families each offer a different combination of features so no one family solves every system need. This is true for the embedded system support functions that help designers reduce the complexity of their systems. On-chip functions such as PCIe endpoints, blocks of SRAM, DSP blocks (configurable multiplier-accumulator functions), and the programmable logic fabric are common to many of the flash- and SRAM-based FPGAs.
However, more unique functions such as embedded processors, memory controllers, multi-gigabit/s SERDES ports, and dedicated support for data encryption/decryption are limited to select devices.
Power consumption in both active and standby modes can often be a deciding factor in FPGA selection, especially if the end system has to operate at low power levels or needs to run as long as possible on battery backup during a power outage.
Figure 3 highlights the different operation modes that an FPGA goes through during system start-up and continued operation. The flash-based devices offer many power-saving advantages vs the SRAM-based FPGAs since flash FPGAs have no inrush power and configuration power and can operate at a significantly lower active power than the SRAM-based FPGAs.
Growing connectivity is forcing designers to make additional efforts to keep the systems secure against hacking as well as provide the ability to securely communicate with other systems through the Internet.
However, once a system connects to the Internet, it becomes a target for hackers who might try to compromise the system by downloading new configuration data. To prevent this from happening, some FPGAs now include security subsystems that ensure only authorized configuration code or control programs are loaded and executed – this process is referred to as “secure boot.” Built-in countermeasures that prevent physical attacks such as anti-tamper and zeroization of the memory are available, and with flash-based FPGAs, keys and critical data can be kept confidential using on-chip secure flash storage.
Today’s FPGAs can include hardwired systems security blocks that perform NIST-certified AES256, SHA256 and elliptical curve cryptography algorithms to deliver real-time encryption/decryption. In addition, a random number generator and physically uncloneable function (PUF) can be included The PUF can be used to generate the private key in a public key infrastructure (PKI) scheme that only the device knows, thereby simplifying user key management and, of course, random numbers are used extensively in cryptographic protocols. Today’s security-centric SoC FPGAs can be programmed only with an authenticated, encrypted bitstream. Some designers integrate an industry-standard microcontroller and subsystem with built-in secure capabilities, as well.
Many other features of today’s FPGAs provide system solutions for applications in the networking and data communications markets. For example, the inclusion of on-chip 5 Gbit/s SERDES ports and multiple PCIe serial interfaces provides high-bandwidth interfaces for applications such as XAUI/XGXS and other high-speed networking interfaces. By including enough general-purpose I/O pins, today’s FPGAs also provide the necessary ratio of I/O pins to core logic, thus assuring that designers don’t have to select a larger FPGA than necessary just to get a higher I/O count.
Lastly, adequate static RAM and embedded non-volatile memory (at least 5 Mbits of SRAM and 4Mbits of eNVM) gives designers plenty of storage for register files, caches and buffers that, in conjunction with the integrated DSP blocks, allows FPGAs to implement complex signal processing algorithms and process network protocols, handle packet inspection, and other network functions.
Flash-based FPGAs offer a wide range of features that allow designers to craft highly-integrated system solutions that reduce system costs, minimize printed-circuit board area, minimize power requirements, and still deliver performance gains over SRAM-based FPGAs.
Tim Morin , director of marketing at Microsemi , has held numerous roles during his eight-year tenure at the company, including Product Planning for SmartFusion, SmartFusion 2, and IGLOO 2 FPGAs. Prior to Microsemi he worked at Atmel Corporation in various marketing roles, and for Texas Instruments Defense Systems and Electronics Group.