Flex Logix turns FPGA/MCU-based SoC design upside down - Embedded.com

Flex Logix turns FPGA/MCU-based SoC design upside down


Coming out of its stealth mode, start-up Flex Logix Technologies has just take the wraps off its EFLX FPGA (field programmable gate array) that it says will allow chip makers and equipment manufacturers to update normally fixed functions in silicon at will.

According to Geoff Tate, Flex Logix CEO and co-founder, the company's.EFLX, cores can fit into chips selling for hundreds of dollars to less than one dollar. “FPGA technology has been employed for years in markets where performance requirements are stringent and real-world uses are unpredictable,” he said. “With EFLX cores, we can bring what’s great about FPGAs to a broader spectrum of customers and users.”

The first EFLX offering (Figure 1 ) comprises three cores — the EFLX-100 with 100 4-input LUTs (lookup tables); the EFLX-2.5K with 2,500 LUTs; and the EFLX-10.4K.  Fabricated in TSMC's mainstream 28 nanometer CMOS process, they will all be pre-laid-out, pre-characterized, and provided in GDSII format with an an interface designed to support efficient tiling.

What this means is that a chip designer needing only only 400 LUTs could achieve this by “snapping” four EFLX-100 cores together, or arrange then in almost any configuration, such as a 2×2 square or a 4×1 row on an SoC, depending on what is needed in a design to achieve optimal results.

An individual 2,500-LUT (look up table) core, said Tate. is expected to add less than 15 cents to the total manufacturing cost of a device. Designers will be able to integrate multiple EFLX cores, into multiple circuit blocks in the same design or tiled together to create arrays of 7 x 7 or more EFLX cores for greater performance.

Figure 1. Initial 28 nanometer EFLX core design incorporates a 2,500 look up table array.

Tate said Flex Logix will also develop smaller EFLX cores that will cost fractions of a cent as well as EFLX cores with more LUTs to serve a greater number of applications. The company is in discussions with a number of companies, especially in communications and networking.

The new approach to FPGA integration into MPU-based SoC designs is aimed at reducing chip design costs which have been rising sharply, according to analyst reports. Developing new mask, or circuit pattern, to upgrade a single chip can cost $2 million to $5 million,” said Tate. “Missing product cycles because of design or technology issues can mean millions in lost revenue. Similarly, end-users often have to replace equipment or endure sub-optimal performance because of unanticipated in-field conditions.

According to Tate while standalone FPGAs allow hardware to adapt to new demands and technologies, they add substantial cost. As a result a large percentage are employed only in higher-end markets like aerospace, automotive and medical imaging.  Because FPGAs consist of identical circuit blocks connected through an intricate network, increasing their performance typically means increasing costs and board space.

The Flex Logix cores deal with this issue by using a unique hierarchical network that reduces the length of communication links between logic blocks. It was developed by company cofounders Cheng C. Wang, Fang-Li Yuan while they were graduate students at UCLA. They, along with UCLA professor of electrical engineering Dejan Markovic have received the prestigious Lewis Award for Outstanding Paper at the International Solid State Circuits Conference (ISSCC), for a paper outlining concepts embodied in EFLX.

The CMOS chip they describe in their paper occupies 20.5 square millimeters and incorporates 2,760 fine-grained configurable logic blocks (CLBs) with 11,040 6-input look-up-tables (LUTs) for random logic, basic arithmetic, shift registers, and distributed memories, 42 medium-grained 48b DSP processors for MAC and SIMD operations, 16 32K×1b to 512×72b reconfigurable block RAMs, and 2 coarsegrained kernels: a 64-8192-point fast Fourier transform (FFT) processor and a 16-core universal DSP (UDSP) for software-defined radio (SDR).

Using a mixed radix hierarchical interconnect, said Tate, the chip achieves a 4× interconnect area eduction over commercial FPGAs for comparable connectivity, reducing overall area and leakage by 2.5×, and delivering a 10-50% lower active power. With coarse-grained kernels, the chip’s energy efficiency reaches within 4-5× of ASIC designs.

“Not only does this new architecture reduces overall power consumption and improve performance of SoCs with FPGA and CPU mixes, it also reduces the area required for interconnects by 50% or more as well as the number of metal layers,” he said.

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