A current trend in real-time embedded systems, driven by size, weight, power, and cost concerns, is consolidating many increasingly complex software tasks onto fewer hardware platforms. A single processor must then execute multiple tasks with differing importance,safety, or certification requirements—creating a mixed-criticality system. These requirements are often specified using criticality levels,such as the five levels (A-E) used in the DO-178C avionics standard.
A task is considered hard real-time if it must never miss a deadline, and soft real-time if deadline misses maybe acceptable. In this paper, we assume each criticality levelhas a requirement regarding deadline importance, with high criticality tasks classified as hard real-time and low-criticality tasks classified as soft real-time.
High criticality tasks require spatial and temporal isolation guarantees for independent verification, and the task set should efficiently utilize hardware resources. Hardware-based isolation is desirablebut often underutilizes hardware resources, which can consist of multiple single-core, multicore, or multithreaded processors. We present FlexPRET, a processor designed specifically for mixed criticality systems by allowing each task to make a trade-off between hardware-based isolation and efficient processor utilization. FlexPRET uses fine-grained multithreading with flexible scheduling and timing instructions to provide this functionality.
FlexPRET supports an arbitrary interleaving of threads, controlled by a novel threadscheduler. By classifying each thread as either a hard real-time thread (HRTT) or a soft real-time thread (SRTT), FlexPRETprovides hardware-based isolation to HRTTs while allowing SRTTs to efficiently utilize the processor.
Each thread, eitheran HRTT or SRTT, can be guaranteed to be scheduled at certain clock cycles for isolation or throughput guarantees. If no thread is scheduled for a cycle or a scheduled thread has completed its task, that cycle is used by some SRTT in a round-robin fashion—efficiently utilizing the processor.
From the hardware perspective, the presented architectural techniques could be applied to other processors, or FlexPRET could bea core in a multicore system that uses a predictable networkon-a-chip for communication.
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