A family of flexible 10-Gbit/s multi-queue flow-control ICs make use of clock rates up to 166 MHz DDR (Double Data Rate) and offer up to 10 Mbits of storage density. Configured with a by-40 bit data bus, these multi-queue flow-control devices can handle the needs of next-generation, high-throughput platforms, such as W-CDMA base stations, large-scale data-acquisition systems, high-speed image processing equipment, and 10-Gbit/s Ethernet switches and routers. This also includes the emerging Jumbo packets, as large as 9 kbytes.
For systems running at 10 Gbits/s or higher, designers can use the devices for prioritization and quality-of-service on ingress or egress. And due to the high throughput supported, the parts can be employed with just one queue, similar to a large, DDR FIFO memory, to support fast buffers in the data stream. A unique feature mode lets users monitor any of the pins on a given packet and gives the designer time to react to any indication, such as a customer definable end of packet (EOP). The parts are flexible enough to remember the EOP mark and ensure no data is lost when the queue is accessed again. An internal PLL enables the device to offer a source synchronous output read (echo) clock that center aligns the output read data for downstream devices. This feature decreases read data access time to 0.5 ns. Prices range from $81.50 to $105.00 each in high-volume quantities. Additional product information can be found at www.idt.com/products/fcm.html.