As digital signal processing chips gain momentum in personal electronics and emerging applications such as voice-over-Internet Protocol (VoIP), vendors are boosting the speed and memory density of their device families.
Freescale Semiconductor Inc. (Austin, Texas) has expanded its solutions for VoIP system designs based on the StarCore DSP technology. Freescale will be going head-to-head against the C54x, C55x and C64x DSP families from Texas Instruments Inc. and the Blackfin line from Analog Devices Inc., among others.
Freescale's MSC711x DSP family, for example, offers the price/performance, high integration and connectivity required by VoIP system manufacturers, the company said. The five devices in the family, which vary according to customer-driven peripheral sets, are based on a synthesizable language written in high-level hardware-description language. The chips boast low power consumption estimated between 250 and 400 milliwatts, and they come in lead-free 17 x 17-mm 400-pin MAP-BGA 0.8-mm-pitch packages. Depending on the channel density requirement, the MSC7116, MSC7115, MSC7113, MSC7112 and MSC7110 support VoIP systems from four to 128 channels in fractional or multiple T1/E1 increments.
The MSC7115, MSC7112 and MSC7110 specifically target low-cost enterprise VoIP, Internet Protocol PBX and network edge and access applications with 408 kbytes total memory and three TDM Interfaces; 216 kbytes total memory and two TDM interfaces; and 88 kbytes total memory and one TDM interface, respectively. Designed to provide higher-speed interconnects, higher performance, higher integration and lower system-level cost, the MSC7116 and MSC7113 are tailored for developers of Ethernet-only equipment. Double-data-rate DRAM, the ideal memory controller for the current commodity memory technology, enables the entire MSC711x family of DSPs to deliver higher memory bandwidth, lower system cost and single-component availability for memory-intensive applications, the company said. For more details on the Freescale family, see Freescale’s MSC711x devices.
The block diagram below shows the functions packed into the Freescale MSC711x DSP based on Starcore technology.
Freescale's Smart Packet Telephony reference designs, based on the company's PowerQuicc processors and StarCore DSP technology, are designed to accelerate time-to-market and provide a scalable solution from fractional T1/E1 to OC-12 and beyond, as well as network connectivity with Ethernet, Gigabit Ethernet, Utopia, TDM and RapidIO.
For its part, Analog Devices (Norwood, Mass.) has been targeting IP-enabled set-top boxes with its BlackFin DSP-based processors. Along with video-enabling features such as DDR memory support and four video ports, the ADSP-BF566-eM30 dual-core processor embeds 10/100 Ethernet media-access control (MAC) with a media-independent interface, a 32-bit external-bus interface, 32-bit, 66-MHz PCI support, Atapi/ATA and a host-port interface.
On top of the embedded hardware, ADI says it has designed its software architecture to take maximum advantage of the BlackFin's RISC and DSP capabilities. For example, when resources are required for application processing, 90 percent of the processor is applied. Alternatively, when resources are needed for media processing, all required resources are applied. The combined hardware-and-software architecture reduces overall cost and software complexity, said Bill Gotschewski, manager of BlackFin general-purpose processing, while allowing carriers to upgrade set-tops as needed. For more details, visit ADI DSPs.
Texas Instruments (Houston) has been busy enhancing the performance of its DSP families in recent months. For example, TI boosted the speed of its TMS320C6412 to 720 MHz. The 500- and 600-MHz versions of the DSP family, launched in 2003, have been in full production. Among the types of systems that can benefit from the higher performance of the C6412, according to TI, are networked applications such as voice-over-packet and video servers; high-resolution and industrial imaging applications; and office machines such as printers, scanners, copiers and faxes.
Based on TI's highest-performing DSP core architecture and 130-nanometer CMOS process technology, the 720-MHz C6412 achieves 2,880 million 16-bit multiply-accumulate operations (MMACs) per second. This new performance level enables developers of high-end, multichannel communications systems to replace multiple DSPs in production systems with a single C6412, TI said, and utilize an on-chip Ethernet MAC and PCI interface for efficient communications. “With the emerging desire of telecom providers to add video processing to their existing voice applications, the extra 120 MHz provided in TI's new chip positions it perfectly to fit the triple-play [voice, video, data] usage-model forecast for the coming year,” said Avi Fisher, chief technology officer of Surf Communication Solutions. “The increased performance of the new DSP enables Surf to either increase our densities by a factor of 20 percent and increase our channel density from 32 universal ports [voice, fax, data] to 38; or enable 32 universal ports alongside video-transcoding ports.” The C6412, Fisher said, “allows simultaneous processing of all these transmission types on the same DSP.”
The device integrates an optimized mix of peripherals that provide design flexibility and fast data throughput while saving external components and board space. Peripheral functions include an on-chip Ethernet MAC, peripheral component interconnect (PCI) port, host port interface (HPI), enhanced direct memory access (EDMA) controller supporting up to 64 independent channels, and 64-bit external memory interface (EMIF). To further speed processing, the device also integrates generous on-chip random access memory (RAM), featuring 256 Kbytes in level 2 cache. For more details on the units, Search TI devices.
More recently TI enhanced its TMS320C6418 running at 500 MHz by extending its operating temperature range to – 40 to 105 degrees C, enabling applications to function under extremely harsh environmental conditions. Featuring 512K bytes of level-two (L2) cache, the C6418 device at 500 MHz can achieve an impressive 2000, 16-bit million multiply accumulate cycles (MMACs) per second or 4000, 8-bit MMACs per second peak performance. An integrated Viterbi coprocessor (VCP) offloads heavily used operations from the core, boosting performance by as much as 30 percent in applications such as Digital Terrestrial Television Broadcasting (DTTB) and Direct Broadcast Satellite (DBS) services. For more details, see ti’s TMS320C6418.