The industry has made significant progress in addressing the need for system languages, yet public discussion has increasingly revolved around controversies related to standards-making procedures. Instead of more debate on administrative issues, designers urgently need critical capabilities such as more advanced verification features and more powerful assertions.
In reality, an emerging confluence of standards promises to deliver these much-needed capabilities to the design community. Accordingly, the discussion about systems languages should more properly focus on the ability of these standards to deliver results to designers urgently looking for more effective design solutions. In particular, the ability of these languages to work together in a coherent fashion gives the best shot at providing a useful design and verification solution.
It is time to bring the discussion back to the substantive merits of the system design language standards. These standards evolved in response to a growing level of design complexity that has eclipsed the capabilities of traditional RTL simulation-based methodologies and still impedes design progress today. Rather than replace existing languages or methodologies, however, these languages promise to enhance existing development capabilities and help coalesce them into a consistent framework for design and verification.
The combination of SystemVerilog, SystemC and the Property Specification Language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs with critical capabilities including advanced verification features such as solvers, constrained random testing and more. They bring powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.
Assertions offer designers an increasingly important tool for verification of complex systems. Assertions are statements that specify that specific conditions, or sequences of conditions, in a design are true and generate an error message if not.
Although individual languages offer assertion capabilities, PSL provides a more general class of assertions tied to formal verification methods. As such, this standard will not only deliver a consistent method for expressing assertions across multiple languages, but also help designers combine methodologies for traditional verification and formal verification.
In contrast, SystemVerilog supports assertions in its SVA notation. These assertions, while similar in intent and loosely derived from PSL, are more closely tied to the process model of Verilog. This is an advantage for users of this single language, but a limitation for users who need the flexibility provided by multi-language platforms.
For their part, the two dominant system languages address different, real needs in the design community. SystemVerilog provides hardware designers with the ability to build on the strengths of Verilog to reach up to higher abstraction levels, while providing features for more concise expression of code. It promises productivity gains needed to help designers tackle design and verification of next-generation system-on-chip (SoC) devices.
SystemC provides a complementary capability for system designers looking to elaborate their system-level designs into detailed implementations. It builds on system designers' natural choice of C/C++, particularly for complex software-rich systems, and extends these familiar standards with features needed for hardware design and verification. SystemC promises significant productivity gains for development and reuse, enabling useful software development well in advance of detailed RTL implementation.
For all of the real strengths of these new languages, their successful deployment depends on their ability to coexist in real development environments, and the writers of the standards have provided the key enablers for interoperability. SystemVerilog provides an interface between RTL and gate-level design to high-level descriptions written in C, C++ or SystemC. And SystemC Models of Computation (MOCs) provide a bridge to more detailed representations including RTL.
In fact, both SystemVerilog and SystemC meet in an intermediate layer of abstraction, where SystemC code and SystemVerilog RTL can intermingle within transaction-level models (TLMs). Using TLMs, engineers work with abstractions that can be elaborated later to implementation details.
For simulation of bus operations, for example, engineers can create a bus TLM that specifies the transactions needed to provide bus function. Rather than model individual signals with pin-level RTL descriptions of bus operations, the corresponding TLM groups together signals, reducing the size and complexity of the modeled subsystem. Such abstractions offer a more compact, easily understood representation that runs dramatically faster in simulations than corresponding RTL models even when using cycle-accurate transaction models.
The requirement to support more powerful modeling and verification capabilities lies at the heart of the new system design languages. With the emergence of SystemVerilog, SystemC and PSL, engineers will have the ability to mix legacy HDLs with bottom-up SystemVerilog designs and top-down SystemC designs. Along with the capability to interlink verification modeling capabilities available with these languages, designers will be able to verify system operation using transaction-level modeling that interacts with blocks designed in either language.
Indeed, successful SoC design and implementation depends on the ability to combine the strengths of each language in developing a complex design. In combination, SystemVerilog, SystemC and PSL represent a unique design framework able to deliver the diverse modeling and verification capabilities for emerging designs.
Designers are already exploiting high-level design languages, and PSL is rapidly gaining momentum. Due to the size and complexity of these new languages, the industry will need to agree to adopt common pieces for interoperability. This will simplify the user's task in choosing the appropriate subsets that make sense for their specific needs. Whether these subsets emerge informally or are developed by industry groups, they will be needed for successful implementation and adoption of the design and verification methodologies based on the emerging language standards.
Rather than polarize the industry, the emergence of SystemVerilog, SystemC and PSL should galvanize vendors and users alike to find the best ways to exploit these complementary standards. The emergence of these multiple standards promises to reinvigorate important industry groups such as the Design Automation Standards Committee (DASC) with a cross-fertilization of design ideas as the industry explores further opportunities for language synergy and interoperability.
For designers, these standards represent a vital enrichment of capabilities available for complex designs, rather than an “either-or” choice. For all of us, the promise of these standards demands a return to the industry's traditional focus on the important issues facing designers.
Victor Berman is Group Director of Language Standards for Cadence Design Systems.