Cambridge, UK A UK company has developed a JTAG debug scheme that reduces the number of device pins required for debug from five to one. Debug Innovations' J-LINK system, which was architected and designed by Dave Adshead, who was previously the chief debug architect at ARM, will be demonstrated at Embedded World 2004 in Nürnberg (Feb 17 to 19).
Since the emergence of the IEEE 1149.1 JTAG standard, all chips with boundary scan have allocated five device pins to enable access to the boundary scan circuitry. This has facilitated both board test and device testing using scan test methods. Software debug architects have adopted this same system to gain access to the device for software development and debug.
While this has been the norm for over a decade, the push for greater functionality and smaller footprint devices while still maintaining a high degree of access for debug and test has put pressure on chip manufacturers to increase device pin count. This in turn pushes up the size and cost of a device and/or decreases the pitch of its pins.
This has lead to a 'debug dilemma' in which high performance processors require a comprehensive test and debug system but the five debug pins required can usefully be used for other functions. Reducing the number of pins required fro JTAG to on is of particular importance to manufacturers of low pin count microcontrollers.
The J-LINK system consists of a small piece of on-chip logic known as the 'interface circuit' and a 'converter box' which interfaces J-LINK to standard JTAG testers or in-circuit emulators (ICEs). It enables designers to test and debug devices with standard JTAG interfaces using one device pin.
The converter box circuitry can be built into ICEs and the design of J-LINK provides backward compatibility with the IEEE JTAG standard to allow ICE manufacturers to add J-LINK support without adding extra connectors or users having to know which standard is being used by a particular chip or board.
Adshead is credited as the designer of the ARM ICE product Multi-ICE and has provided years of debug and JTAG consultancy. J-LINK is being offered as licensable IP to both chip makers and debug hardware manufacturers.
J-LINK converter boxes will also be available ready built for use with ARM's Multi-ICE or compatible JTAG ICE products.