Forum highlights silicon roadmap - Embedded.com

Forum highlights silicon roadmap

BRUSSELS — One walks away from the Imec Technology Forum with a slightly clearer sense of the semiconductor road map and its drivers, including the somewhat overhyped Internet of Things.

After several talks and interviews, some of the confusion from the marketing of node names briefly dissipates, and some of the angst about the end of the silicon world eases. Unfortunately, the process starts as it often does these days with a dose of strong medicine, this year delivered by Globalfoundries’ chief technologist Gary Patton among others.

“The reality is scaling has slowed dramatically, these node names are a marketing tool and the value proposition has reduced considerably,” Patton told attendees.

The days of 35% lower costs and 20% greater performance every two years “ended at the 20nm node when the need for double patterning created significant cost increases, then we added FinFETs and called it 14/16nm, but really it’s a retrofit,” he added, debunking today’s leading-edge processes.

Not stopping there, Patton called the 10nm process his rivals TSMC and Samsung are racing to deliver “more of a half node.” By contrast, “at 7nm there’s hope for a full node, measured from 14/16,” he said.

Later in the day, Reinhard Ploss, the chief executive of Infineon Technologies, summed up the outlook for Moore’s law in a sentence. “Sooner or later you have to put in an unbelievable amount of effort to take a tiny step,” he said.

“We work harder for less improvement in power, performance, price and area,” added Roawen Chen, senior vice president of global operations at Qualcomm and a veteran process technology specialist.

Chen pointed to a widening gap between version 1.0 and 2.0 of foundries’ process development kits that designers at Qualcomm and elsewhere depend on to get a leg up on leading-edge technology. “Silicon delays are growing due to limited predictable data, and execution risks are rising,” he added.

A researcher tests a new process step in Imec's fab. (Images: Imec)

A researcher tests a new process step in Imec's fab. (Images: Imec)

Ivo Raaijmakers, chief technologist of equipment maker ASM International, offered a slightly more upbeat view

“The industry will find a way to continue scaling, not a classic Denard scaling, but there are many innovations in the pipeline…so maybe the growth rate will decrease a bit and the cadence of new nodes will decrease…but we don’t see this as a downward spiral, just a shift from nodes maybe every three years instead of two,” Raaijmakers said.

He pointed to his company’s work in atomic layer deposition of chemicals as one of the great hopes for scaling, but noted such exotic techniques require more spending on R&D. And he acknowledged the out-of-whack marketing trying to paint a pretty face on the reality. “When you look at a 14nm process, it’s hard to find anything that’s 14nm there,” he joked.

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