Four-lane PCIe bridge reduces design time by up to 80% - Embedded.com

Four-lane PCIe bridge reduces design time by up to 80%

Burlington, Ontario—Gennum Corp. has unveiled a PCI Express (PCIe)-to-local bus bridge chip that offers four lanes at 2.5-Gbit/s or 10-Gbit/s in each direction.

According to Gennum, the GN4124 enables designers of high-speed embedded applications to leverage the full potential of the PCIe standard with a low cost, turnkey solution and speed time to market by up to 80 percent. The GN4124 PCIe bridge offers three to six times the performance over legacy bridge and endpoint products by providing 1600MB/s burst throughput and full duplex operation, Gennum said. This enables such capabilities as supporting multiple channels of uncompressed HD or 1080p video, meeting the demands of higher data rate applications in video broadcast, medical, data communications and industrial control markets.

The integrated functionality of the GN4124, which is bundled with Gennum's royalty-free local bus FPGA IP, incorporates the PCIe physical layer and digital controller on-chip, eliminating the need for this functionality to be integrated into a stand-alone, complex and expensive FPGA.

Pricing: Expected to be $20 per unit based on 10K quantity volumes.
Availability: Sampling with full production slated for Q4 2008.
Product brief: Click here.

Gennum Corp., www.gennum.com

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.