FPGA board has short cycle times and low latencies - Embedded.com

FPGA board has short cycle times and low latencies

LONDON — The DS5203 FPGA board from dSPACE can be used directly at the I/O interface. It provides the flexibility and performance needed for signal preprocessing and for model calculations with high dynamics requirements.

Typical application areas include the development of closed-loop controls based on in-cylinder pressure, the analysis of knock signals, and the management of highly dynamic effects on power stages, which is absolutely essential for tasks such as developing electric motors.

The board has a programmable Xilinx Virtex-5 SX95 FPGA and complements the core of a dSPACE real-time system, such as the DS1006 processor board, by performing specific calculation tasks with extremely high cycle-time requirements.

The DS5203’s FPGA is directly connected to the I/O, so the entire bandwidth of converters can be used with minimum latencies, and very fast control loops can be implemented.

The Xilinx System Generator (XSG), a Simulink blockset for configuring Xilinx FPGAs, is a convenient way to configure an FPGA by graphical modeling. dSPACE provides both the hardware (DS5203 FPGA Board) and the software (RTI FPGA Programming Blockset1)) to connect the XSG model to the FPGA's interfaces.

The blockset eases the connection to the I/O driver components of the I/O boards and to model the connection to a processor board such as dSPACE's DS1006, the central board for calculating complex models. When the FPGA board is used, the synthesis, build, and programming of the FPGA or processor can be run directly from Simulink for convenient FPGA handling.

The FPGA application can be simulated offline, before it is loaded onto the real-time system. Users can also investigate the interaction of the processor and the FPGA model during the offline simulation. The ability to perform simulations at an early stage means that users can react flexibly to changing requirements, for example, when using new interfaces or when adapting model parts that were placed on the FPGA.

Further Information on www.dspace.de.

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