A family of fractional resampling architectures for FPGAs can perform up- or down-sampling of high-speed digital signals. The designs offer a flexibility in the design of the resampling filter and better dynamic range, when compared to designs based on traditional architectures. They can also efficiently handle thousands of channels simultaneously and independently.
Fractional resampling is a signal processing function that enables the manipulation of the signal sample rate, so that it can be p matched to the requirements of subsequent processing. This has many applications, but is particularly relevant for matching symbol and sample rates in digital receivers, enabling the modulators and demodulators to be simpler and cheaper. Examples include telecommunications modulators and demodulators, image and video processing, audio processing, and interfacing to hardware components with fixed sample rates.
The architecture is scalable, and can support resampling of one or thousands of channels simultaneously, while maintaining efficient use of silicon resources. The resampling rates can be selected with high precision, and allow selection of output sample rates with a resolution less than 1 Hz. When operating on multiple input channels, the architectures treat each channel independently, allowing different input sampling rates, and rate changes for each channel. Also, the rate change required for each channel can be updated at run time, without affecting the operation of other channels. For further information, go to www.rfel.com.