Freescale drives into heads-up auto displays with triple core MAC5705

At its Technology Forum this week, Freescale Semiconductor continued its efforts to penetrate the infotainment segment of the automotive electronics market with the introduction of its MAC57D5xx MCUs, scheduled for availablity in sample quantities in June.

According to Ray Cornyn, vice president of Product Management and Global Marketing for Freescale’s Automotive MCU business,  high-end automotive instrument clusters typically incorporate multiple external components, including a main processor, graphics unit, external SRAM, and dedicated circuitry to manage heads-up display warping and other sophisticated functionality. The cost and complexity of integrating these multiple parts previously restricted this functionality to the premium car segment. .

“With automotive system integration at an all-time high, OEMs and their suppliers are focused on consolidating large amounts of driver information and increasing the quality of graphics in dashboards, while keeping safety and security as the first concern,” he said.

To deal with these issues Freescale Semiconductor has introduced as triple-core, single-chip architecture that the company claims offers more than 1.7x higher performance than any currently available automotive instrument cluster MCU.

Offering just about everything the designer of a next generation auto infotainment display cluster would want, the new ARM based SoC (Figure 1 below ) features 2D graphics accelerators, HUD warping engine, dual TFT display drive, integrated stepper motor drivers and a powerful I/O processor..

Figure 1. Triple core architecture also incorporates 2D graphics accelerators, HUD warping engine, dual TFT display drive, integrated stepper motor drivers and a powerful I/O processor..

The new family said Comyn, supports up to 2 WVGA resolution displays, including one with in line Head Up Display (HUD) hardware warping. Graphics content is generated using a powerful Vivante 2D GPU (supporting OpenVG1.1) and the 2D Animation & Composition Engine (2D-ACE), which significantly reduces memory footprint for content creation. .

The architecture's embedded memories include up to 4MBytes Flash, 1MB SRAM with ECC and up to 1.3MB of graphics SRAM without ECC. Memory expansion is available through DDR2 and SDR DRAM interfaces while two flexible QuadSPI modules provide SDR and DDR serial flash expansion.

In response to the growing desire for security and safety, he said, the MAC57D5xx family integrates Freescale’s latest SHE-compliant CSE2 engine and delivers support ISO26262 ASIL-B functional safety compliance. To further securirity and safety, the new architecture supports concurrent – and separate – operating systems on each of the devices’ three cores, allowing, for example use of the AutoSAR OS on the ARM Cortex-M4 core, and a graphics OS on the ARM Cortex-A5 core..

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