Freescale to demo Cortex-M0+ Kinetis devices at DESIGN West - Embedded.com

Freescale to demo Cortex-M0+ Kinetis devices at DESIGN West

Freescale Semiconductor is to demonstrate its Kinetis L series microcontrollers (MCUs) built on the ARM Cortex-M0+ processor at DESIGN West in San Jose, California, with alpha sampling due to start in the second quarter of 2012.

Freescale says the ability to demonstrate these devices is possible due to its close partnership between ARM during the Cortex-M0+ core development process and as a lead partner provided  input that helped ARM define and develop the processor.

The devices are slated for applications such as domestic appliances, portable medical systems, smart meters, lighting, power and motor control systems.

“Our close partnership with ARM throughout the design and development of their new core has positioned us as the first MCU supplier to produce and demonstrate an MCU based on the Cortex-M0+ and continues our strategy of driving to market new products based on the ARM architecture,” said Reza Kazerounian, senior vice president and general manager of Freescale’s Automotive, Industrial and Multi-Market Solutions Group.

Mike Inglis, executive vice president and general manager of ARM’s Processor Division, added “With the addition of the L series to their Kinetis line, Freescale is creating one of the industry’s broadest, most scalable ARM Cortex-M MCU portfolios, ranging from very low-cost, entry-level products based on the ARM Cortex-M0+ processor, up to 4 MB, 200 MHz devices based on the Cortex-M4 processor.”

Manufactured using Freescale’s low-leakage, 90 nm thin film storage (TFS) process technology, the Kinetis L series will have a selection of on-chip flash memory densities and analog, connectivity and HMI peripheral options.

Upward migration through the Kinetis portfolio is available via compatible Kinetis K series devices (built on the ARM Cortex-M4 processor) that provide access to DSP performance and advanced feature integration.

The ARM Cortex-M0+ processor includes a reduced two-stage pipeline, allowing faster branch instruction execution, single-cycle access to I/O and critical peripherals, optimized access to program memory, linear 4 GB address space that removes the need for paging, reducing software complexity and ensuring a more 8-bit-like user experience and a micro trace buffer, providing a low-cost trace solution that allows faster bug identification and correction without the need for additional I/O resources.

Freescale will demonstrate the ARM Cortex-M0+ core at its exhibition booth #1604 at DESIGN West, March 26-29 at the San Jose McEnery Convention Center.

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