Fun With ASICs - Embedded.com

Fun With ASICs

Mojy Chian, Richard Cliff, and Jeff Watt have an interesting article atEDN.COM entitled “Achieving First-Time Success at 40 nm , “in which they describe how Altera is migrating their FPGA line to the40 nm process node.

The sidebar gives the percentage of ASIC design starts at variousgeometries, starting from bigger than 0.5 micron in 2002 to projectionsof 22 nm in 2011. At that point the engineering cost on a bleeding-edgeASIC project will exceed $100 million, a rather horrifying number.

Projections are always fun, and it's entertaining though dangerousto extrapolate from both current data and other people's projections.So I fit curves, selected somewhat arbitrarily based on “looks like agood match,” to the article's data:

The pink line is the process geometry, and the extrapolation lookslike a pretty good match to historical data from the last half-dozenyears. Between 2002 and 2008 the effect of Moore's Law is simplystunning. No other industry has achieved any similar sort ofimprovement in anything over such a short period.

After 2014 it's hard to extract much from the graph, but around 2018this curve predicts features will be about an angstrom across, roughlythe size of a single atom. That's absurd, of course, though today gateoxides on some parts are just an astonishing few atoms thick.

But clearly something has to happen before we get to that node. Itwon't be quantum computing because even the optimists figure that'syears off. Maybe Moore's Law will finally sputterout. Wags havepredicted its demise for years, only to be proven wrong every time.

Around the same time engineering costs would, if these trendspersist, reach about a cool billion bucks. As Senator Everett Dirksenreputedly said, “A billion here, a billion there, pretty soon you'retalking real money.” Few products will tolerate $10E9 NRE costs.

I carried the projection out further. In about 50 years the cost ofjust one ASIC project will exceed the United State's current GDP.

It'll be a hell of a product, though.

Those these numbers are “projectio ad absurdum.”  But they doshow an approaching moment of inflection where some significant changein high-end semiconductors will be required, a change that'srevolutionary rather than additional incremental improvements. Somescaling hard limit surely exists, be it the Planck length or, morelikely, at the atomic level. And the atomic level just isn't that manyyears away.

Jack G. Ganssle is a lecturer and consultant on embeddeddevelopment issues. He conducts seminars on embedded systems and helpscompanies with their embedded challenges. Contact him at . His website is .

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