Many different broadcast video studios in the world are currently operating in different formats, some of them analog, some digital. There are multiple High Definition Television raster formats in use in the USA today. If you tried to count the number of different raster formats covered by the SMPTE292M HD standard, you would run out of fingers, and toes. One might make the assumption that television broadcasters are anarchists, who revel in the chaos of doing things in a different way from the next guy.
Closer examination reveals a whole different world. Within any studio there are many different signals, and they are all kept synchronized in lock step with one another. In video parlance, they are genlocked. Genlocking allows for easy switching from one signal to another (We'll be back after these brief messages) without disrupting the synchronization circuits that are in the viewers' receivers.
In order to do this, it requires that any signal coming in from an outside source be genlocked to the rest of the signals in the studio. Most studios use an analog signal as their timing reference signal, and the timing information needs to be extracted from this signal to allow it to be used to genlock the incoming signal. Far from anarchists, the signals in a TV studio act like synchronized soldiers in a parade, all saluting the great reference signal.
When a new signal is brought into a studio, whether it is coming from a satellite receiver, a camcorder, or any other source, the first thing that is done is to synchronize it with the rest of the signals in the studio. In order to do this, a GENLOCK circuit is used.
Figure 1: GENLOCK block diagram
In Figure 1 there is the block diagram for a Genlock which takes an SDI (Serial Digital Interface) input signal, and synchronizes it with an analog reference that is being supplied. We will look at this genlock application in detail, and look at the design considerations for each of the six blocks.
The SDI inputs on video broadcast equipment typically support long cable lengths — over 140 m for High Definition signals, and over 300m for Standard Definition signals. In order to support long cables, there needs to be a cable equalizer.
The key to being able to extend the length of cable is understanding what the cable does to the signals passing through it. Electrical cable generally consists of a conductor such as copper, with an insulator surrounding it. For the purposes of this paper, our cables always have two conductors, or a conductor and a ground. Ideal cable would be made from an ideal conductor with no loss, and would have a perfect insulator coating it. In reality, the conductor is not perfect, and has some resistive loss. This is usually specified on a cable datasheet in units of ohms/unit length. For Belden 1694A (a common coaxial cable used in the video industry) this is about 10-ohms/1000 ft.
The resistive loss of a cable is primarily of interest when one is sending very low frequency (or DC) signals, over long distances, and as a rule of thumb is an issue when it is of the same order of magnitude as the impedance of the load — therefore if our cable has a 75-ohm load, since it has a resistive loss of 10-ohms/1000ft, then at lengths greater than about 75,000ft, or 25000m, we need to be concerned about resistive loss. By the time we get to those cable lengths, we have bigger problems to worry about. The cable manufacturer has the ability to lower the resistive loss by using a more exotic conductor (silver vs copper for example), or by using a thicker conductor, either one of which will result in a more expensive cable.
In most real world systems, the data rates are high enough so that the AC attenuation in the cable becomes an issue well before the DC attenuation. When a DC current is passing through a cable, the current flows with a constant density through the entire cross section of the cable. When an AC current is flowing through a conductor, it tends to flow mostly on the surface of the conductor — or skin. This is known as the skin effect.
More precisely, the skin depth d is given by:
where d is the skin depth, and is the depth into the conductor at which the field strength has decreased by a factor of e, s is the conductivity of the conductor, w is the frequency of the AC field and m 0 is the permeability of free space. Skin effect means that for the higher the frequency of the signal, the smaller the effective cross section of the cable is.
NEXT: EYE PATTERNS, DESERIALIZER, SYNC SEPARATOR The primary way in which the skin effect will affect us is that as the frequency increases, a smaller and smaller portion of the cross section of the cable will be carrying the signal, so there will be greater signal attenuation at higher frequencies than at lower frequencies. The response curve for this loss will be proportional to the Ö w which makes it difficult to compensate for with standard types of filters. This response curve can be seen in Figure 2
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Figure 2: Belden 1694A frequency response
Although seeing the attenuation with frequency is helpful in designing the complementary filter that we will need to recover the signal, for most of us, the image that we want to see is the eye diagram — is there an opening big enough to recover the data? Figure 3 shows the eye diagrams for a 1.5Gb/s signal (an HD-SDI signal), after it has gone through various different lengths of cable.
Figure 3: Oscilloscope traces of an HD-SDI signal after going through coax cable
Since the basic thing that is happening when we go to longer and longer cables is a low pass filtering, if we apply a complementary high pass filter to the signal, then we should be able to compensate for the cable, and use longer cables with impunity. Unfortunately, there are a few things that work against making this as easy as it sounds. First is the shape of the lowpass characteristic of the cable. Most electronic filters are made using discrete poles and zeroes, for each pole or zero, you can shift the slope of the response by 6dB/octave. The cable has this nasty Ö w response that is difficult to mimic with standard filter architectures. The second issue is that the high pass characteristic requires more and more gain as the frequency gets higher, and circuits don't like to do that.
Another issue with which we must contend is that ideally we would have a filter which would automatically adapt to any length of cable to which it is connected, rather than having one circuit for 20m cables, another for 100m, and yet another for 300m cables. Together these three issues make for a major design headache. Fortunately, there are semiconductor design engineers who have already been inflicted with this set of headaches, and have not only come out alive, but have produced some fine, easy to use equalizers which cost a small fraction of the cost of the cables which they support!
To attempt to match the frequency response of the cable, the designer carefully places the zeroes in his filter such that the resulting response is a close approximation to the Ö w response of the cable. Care must be taken with the design to make these zero locations process independent or the yields of the equalizer would be very low, making the device too costly.
In order to deal with the fact that both high gain and high bandwidth are required at the same time, equalizer circuits are realized in exotic, high-speed processes such as the National Semiconductor 0.25m m BiCMOS SiGe process.
To make the equalizer adapt to various cable lengths, the gain of the high pass filter sections in the chip can be varied via a control voltage, and a feedback loop is established to optimally set this gain. In order to determine the correct amount of gain, the equalizer relies on the fact that it knows what the original launch amplitude and slew rate were — and it adjusts the gain of the equalization such that the output of the filter matches the energy profile of the original signal. This does mean that if the circuit that is driving the signal into the cable is not well controlled, either in its slew rate, or the signal amplitude, then the equalizer is liable not to properly set its gain, and sub-optimal performance will be observed.
An example of one of these equalizers is the LMH0044 cable equalizer. With this part, you can recover signals at data rates of up to 1.5Gb/s through 200m of Belden 1694A cable, better cable and you can go further, lower bandwidths and you can go further.
Figure 4: Equalized outputs
NEXT: DESERIALIZER, SYNC SEPARATOR, FRAME BUFFER and TIMING
Once we have done the hard work of opening the eye of the signal coming in, we have to make sense of the bits that are coming at us, and this is the job of the deserializer. Video images have a very regular, repetitive format, they are composed of individual bits, which are, at the next highest level of organization divided into 10 bit wide words — these words are in turn divided into pixels, a series of pixels comprises a line, a series of lines makes up a field and one or more fields are needed to complete the video frame.
To help sort out this organization, the SMPTE data sends a special sequence known as a Timing Reference Signal (TRS) at the start and end of each line. By detecting this TRS it allows the receiver to figure out both the word and line alignment for the signal. At the end of each line, there are a couple of extra words inserted which tell the receiver what the line number is, and a CRC is also included, so that the receiver can know if it has properly received all of the data in the line. There are a couple of things that can wreak havoc with receivers — DC content, and long periods of time with no transitions. Most communications systems have a way to control this, in the case of the SMPTE 292 serial standard (HD-SDI) it is done with a combination of scrambling and encoding the data.
A good Deserializer will extract all of this information for you, and present you with what you need, which for this application consists of the picture data, and the timing data. A deserializer such as the LMH0031 will do this for us, presenting the picture data on two, ten bit wide data busses, and the timing data, in the form of three digital signals: H (start of a horizontal line), V (start of a vertical interval), and F (start of Frame). If the raster format is not interlaced, then you can get away with just H and V, because V and F are the same thing.
The serial data is brought into the deserializer, it is decoded and descrambled, and then it is analyzed to find the TRSs which allow the deserializer to know how to break the bits into words. The TRSs are further analyzed to extract the timing information allow which is encoded and the data is scrambled, it decodes and descrambled, then the framing is determined so that the deserialized data can be properly word aligned. All this is generally done in the deserializer.
Sync Separator and PLL
Although the video world has gone mostly digital, one area where analog is still very common is in the sync reference signal, which the studio uses to synchronize all of their equipment. The most common sort of reference to use is a video signal which does not have the picture information on it. This will consist of a series of pulses indicating the start of each video line, with a specific pattern that indicates the end of each field or frame. In this block of our Genlock circuit, a sync separator circuit extracts H, V, and F (start of a horizontal line, start of a field, and start of a new frame) from the reference signal, and a PLL circuit generates a pixel clock which is synchronous with the reference signal.
The LMH1981 is a high performance multi-format sync separator that accepts standard analog SD or HD video signals with either bi-level or tri-level sync. It automatically detects the input video format and applies 50% sync slicing to ensure accurate sync extraction even if the input has irregular amplitude, offset, or noise conditions. In order to generate the pixel clock, a PLL should be set up to lock to the Hsync output of the LMH1981 and generate the desired clock frequency, which is typically 27 MHz for SD or about 74 MHz for HD.
Something to consider when using a PLL for clock generation is that the divide ratio can be quite large and reduce loop bandwidth, which could make the PLL quite sensitive to jitter on Hsync. This makes it especially important to select a sync separator with a very low jitter Hsync output.
Figure 5: Block diagram of the PLL generating the Pixel clock
The frame buffer is simply a block of memory that is big enough to hold at least one entire frame of the image. This buffer needs to be dual port, so that the data coming from the deserializer can be written into one side of the buffer, while data can be read from the other side of the buffer, to be fed to the serializer. The buffer is organized the same way that the video image is, with consecutive pixels forming complete lines, and consecutive lines to form the complete frame.
The timing control is the heart of the entire Genlock system. The basic function is to control the writing into the Frame Buffer and the reading from the Frame Buffer. The Timing control needs to keep track of two different timing domains — on the input side it receives the data, the timing information and a clock from the deserializer. This data is written into the Frame buffer, with a series of counters that keep track of the pixel and line information, this data is written synchronously with the clock being recovered from the deserializer.
At the same time, the timing control takes the timing information coming from the sync separator, and the pixel clock these are used with a second set of counters to read data out of the frame buffer. This data is being read out synchronously with the reference sync signal so that the image which was received by the deserializer is now being read out synchronous with the reference — this data, along with the pixel clock are fed to the serializer for output. Although video signals have very tight timing specifications, there will be some difference between the input and the output data rates, which means that eventually the frame buffer will either empty out, or overflow. The timing control circuitry has to recognize this situation, and periodically either repeat a frame, or drop a frame to maintain the timing difference between input and output smaller than the size of the frame buffer.
NEXT: SERIALIZER and WRAP UP
Once the data is read out of the frame buffer, it is in parallel format, and before it can be sent on to the next piece of equipment, it needs to be serialized and formatted to meet the SMPTE 292M HD-SDI standard. From a digital standpoint, new TRS characters are generated and inserted, new line numbers and CRCs are calculated and inserted, the data is then scrambled via the SMPTE scrambling algorithm and converted to NRZI format before being shifted out of a parallel to serial shift register.
The key to doing all of this properly however is that the clock used to shift the data out is clean enough to meet the tight video timing specifications. SMPTE 292M allows no more than 0.2UI of jitter peak-peak on the serialized output, which means that the clock jitter needs to be below about 100ps p-p. Most serializers take as their input clock, a clock which is at the parallel data rate — for HD this would be approx 74 MHz, and then multiply it up to the serial rate of 1.5 GHz.
Most good serializers will use a PLL for this multiplication that will reject some of the jitter in the original parallel clock, but for the best performance, it is best to start with as clean a clock as possible. In our Sync separator/clock generation circuit we generated our pixel clock with a VCXO that tends to have very low jitter, so that added to the jitter rejection characteristics of the serializer will lead to a very low jitter output. Using the LMH0030 serializer, with the VCXO clock source, we could expect our serial jitter to be approx 75ps, well below the 0.2UI limit.
Using a handful of simple, off the shelf components, we can take a radical input video signal, which is marching to the beat of a different drummer, and get it to straighten up, and march with the rest of our signals. This way, we can switch from one program to another without disrupting the image on your screen.
About the Author
Mark Sauerwald graduated from the University of California at San Diego in 1982 with a bachelor's degree in electrical engineering. Since graduation, Mark has been involved in semiconductor components for digital video, first at TRW LSI products, working on A/D converters for digital video, then at Comlinear, later acquired by National Semiconductor. Mark spent a few years working for Gennum Corporation before returning to National Semiconductor where he now works as an Applications Engineer with the Interface Products Group. When not working, Mark is an avid cyclist, and a serious amateur photographer. He can be reached at .