Get more wiggle room in your design’s RMS Phase Jitter budget -

Get more wiggle room in your design’s RMS Phase Jitter budget

Virtually any embedded designer will tell you clock jitter is a moving target, and it’s been that way historically. In short, system and embedded designers continually chase jitter and its ill effects on their designs in the hope that they can significantly minimize it.

That’s a challenging task due to the fact that system data rates are dramatically increasing and timing system requirements are becoming ultra-stringent, thus embedded designers demand that root mean square (RMS) phase jitter be as low as possible. Further, due to ever increasing numbers of battery-operated applications, those designers must carefully scrutinize datasheet specs to assure they’re getting the lowest power consumption accompanying the low RMS phase jitter.

RMS phase jitter is a measure of clock quality in communication systems. For example, the system or embedded designer may deal with a typical protocol like Ethernet or PCI Express (PCIe) stating that the clock quality needs to meet a particular RMS spec. Hence, RMS phase jitter qualifies a clocking device to meet a certain standard.

There are also end points. Every end point will have its own unique jitter requirements. As an example, if an end point is a PCIe end point, it’s going to need a PCIe jitter compliant clock, which is a 1ps RMS jitter requirement for PCIe Gen3 common clock architecture.

Aside from RMS phase jitter, there are several different definitions of jitter. But in general, clock jitter is defined as the deviation of a clock edge from its ideal location, as shown in Figure 1. Getting a good handle on jitter and minimizing it are critical since it plays a key role in a system’s timing budget. In this day and age, with highly demanding system applications and evolving state-of-the-art technologies challenging conventional design practices, jitter and how it is resolved take center stage.

Figure 1: Clock jitter is defined as the deviation of a clock edge from its ideal location.

Unfortunately, in most cases, advanced technologies for combating jitter have not been able to keep up with demanding OEM applications. The biggest issues associated with minimizing jitter involve highly unacceptable power consumption and clock generator products offered in either too large a package or in multiple device packages. Given the ever-shrinking printed circuit board (PCB) real estate, savvy embedded designers seek out smaller, singular packaging to comply with basic design requirements.

Hitting the sweet spot
Smaller packaging is indeed a sought-after feature, especially for growing numbers of mobile and portable applications. However, embedded designers want considerably more, and they’re intent on hitting the sweet spot from a power consumption and performance standpoint among the industry’s mid-range clock generator choices. An added bonus is having a product capable of targeting applications ranging from one to 10 Gigahertz (GHz) Ethernet, while meeting all system RMS phrase jitter requirements the designer requires to comply with his/her overall goal.

Aside from the mid-range versions discussed here, there are higher and lower-end clock generators involving major power consumption and jitter performance tradeoffs. For instance, there are lower-end clock generators for clocking systems that don’t have tight RMS jitter requirements. At the other end of the spectrum, there are high-end clock generators consuming higher power and designed for clocking super low jitter requirements like sub-300 fs for 10 Gigabits per second (G), 40G, 100G Ethernet, and fiber channel applications.

Frequency margining on the fly
One more thing — embedded designers seek the ultimate product in frequency margining. Critically important is the fact that they want their systems to be reliable and robust. They evaluate virtually every parameter of their designs and in so doing, they arrive at certain requirements in terms of specification, and work toward achieving a margin to their specification.

In this regard, most designers require sub-one picosecond (psec) RMS phase jitter performance. In most instances, system designers target one psec RMS phase jitter for one Gigabit per second (Gbps) Ethernet and 10 Gbps Ethernet applications. Many clock generators on the market provide RMS phase jitter performance of one psec or higher.

Consequently, embedded designers are robbed of having an ample amount of margin to their system specification. On the other hand, for example, considerably improved 0.7 psec RMS phase jitter performance from 12 KHz to 20 MHz in a programmable clock generator gives them a 30 percent margin to their system specification, enabling them to have a reliable, robust system.

Leading chipmakers are moving in this direction with integrated and innovative clock generator architectures to reach those new levels of frequency margining. In particular, frequency margining takes on a more streamlined approach.

In this case, embedded designers are looking at changing and increasing clock frequency to determine system robustness for a variety of applications including high-performance consumer, networking, industrial, computing, medical electronics, broadcast video, and data communications.

Normally, with current and earlier generation competitive clock generators, to achieve frequency margining, designers tediously have to go from one clock to another and then to another to change frequency, thus consuming extra design time. However, today’s embedded designer requirements are focused on having multiple different output frequencies and multiple different output types in a single packaged clocking device to effectively meet board space and jitter requirement.

For example, as shown in Figure 2 , IDT’s 5P49V5901ANLGI programmable clock generator hands embedded designers four totally independent frequencies with four totally independent output types and a reference output – all integrated on one chip.

Figure 2: The VersaClock 5 programmable clock generator (5P49V5901ANLGI) provides designers with four independent frequencies, four independent output types, and reference output in single 4×4 QFN.

The four universal output pairs produce independent frequencies up to 350 MHz, configurable as high-speed current steering logic (HCSL), low-voltage positive emitter-coupled logic (LVPECL), low-voltage differential signal (LVDS), or split into two low-voltage CMOS (LVCMOS) outputs (Figure 3 ).

Figure 3: Four universal output pairs produce independent frequencies up to 350 MHz configurable as HCSL, LVPECL, LVDS, or LVCMOS outputs.

The clock generator takes in a single fundamental crystal or reference clock input, generates the four high frequency outputs, and supports from 5 to 350 MHz with 0.7 psec RMS phase jitter.
Clock reference for another system clock
The device providesdesigners a clean copy of the reference output. Most designers clockthese devices from a fundamental crystal. Conversely, the VersaClock 5gives designers a clean copy of that crystal or a sub-400fs copy of thereference clock input. Essentially, the embedded designer gets an extraand free output that can be used to clock another system clock. Forexample, it can clock a CPLD or FPGA.

Programmable clockcircuitry in this instance gives embedded designers the capability toperform frequency margining on the fly. Plus, the bottom line isachieving that 0.7 psec jitter performance inclusive of cross talk dueto the different output frequencies.

Based on a proprietarydesign, this 0.7 psec RMS phase jitter performance is achieved with30-milliampere (mA) core current consumption, thus providing embeddeddesigners with low jitter at low power consumption. Each output can alsobe voltage independent, supporting 1.8, 2.5 or 3.3V on a per outputbasis.

Another similar clock generator on the market consumesdouble the core power at 60 mA and has worse jitter with 1 psec RMSphase jitter on the outputs. Overall power consumption for the IDTdevice in a typical application with four differential outputsoperational is at a low 300 milliwatts (mW).

The 0.7 psec RMSphase jitter equates to greater design margin. In a communicationsystem, jitter affects the overall bit error rate (BER). If jitter ishigh, BER is high, thus affecting overall system performance. The lowerRMS phase jitter hands designers greater margin or wiggle room in theirjitter budget.

Along this line, the 5P49V5901 device has four independent fractional output dividers (Figure 4 )that can be accessed through a serial bus to change output frequencyand thus perform frequency margining. For example, if the designer has a100-megahertz (MHz) output frequency, he or she can step that throughup or down to go from 99 to 101 in any fractional increments.

Click on image to enlarge.

Figure 4: Fourindependent fractional output dividers are accessed through a serial busto change output frequency to perform frequency margining.

Frequency margining for test
Frequencymargining is frequently used for test. OEMs perform frequency marginingin their test phase to test system robustness. Let’s say an OEM has onetarget output frequency such as running their memory at 100 MHz. Intheir test suite, they may want to margin that output frequency toevaluate system robustness by a certain percentage. They may want afrequency margin over a 10% span in +/-1% increments, for example.

Typicallyin an application designers fix a frequency. Margining is generallyused for test in prototype in most applications. Using the 5P49V5901,frequency margining can be performed with no glitches, so designers canliterally step through a given range of frequencies from a centerfrequency and not glitch at all on the output. This is important in manytest setups during prototyping when designers are testing systemrobustness.

Design considerations and tradeoffs
From anapplications point of view, embedded designers take into considerationperformance, power, and space requirements when factoring in clockgenerators. Focus is on clocking end points in a design, such asclocking processors, FPGAs, switches, and bridges. Wherever that clockis going, there’ll be a requirement for jitter on that clock, withdesigners not only checking the jitter requirement, but also carefullywatching their power consumption requirements.

For example, aboard like a PCI plug-in card can handle only so many watts. Let’s sayit’s a 25-watt requirement. The embedded designer must evaluate acomplete package of requirements and understand what is mostcritical. One thing for sure — they have to meet jitter requirement orbit error rates (BER) will go higher and performance is sacrificed.Also, if the design calls for stringent power consumption requirements,the lowest possible power then becomes extremely critical.

Withearlier versions of clock generators, system and embedded designersplaced up to four different clock sources or oscillators on a board tocreate four different high-speed outputs. Today, integration is the nameof the game for clock generators, and now these four clock outputs areon a single chip. Doing this complies with growing OEM demands for lowerpower consumption, board space, and for meeting all performance goalssystem end-points require.

Fred Hirning is Senior Field Applications engineer for Integrated Device Technology (IDT). Previously, he served as digital design engineer at QuadicSystems and later as a senior applications engineer for TundraSemiconductor. Fred received his BSEE from the University of Hartford.He can be reached at .

Baljit Chandhoke is Product Line Manager for Timing Products for Integrated Device Technology (IDT).Since 2011, he has been responsible for new product definition, productline management, and global customer interfacing. Prior to IDT, heworked as a Product Marketing Manager in the Clock and Data ManagementGroup at ON Semiconductor. Earlier he was Senior Applications Engineerat Cypress Semiconductor working on PLL SerDes and video equalizers. Hecompleted Stanford University's Executive Education on Managing Teamsfor Innovation and Success Program in 2014. He has a MBA from ArizonaState University and Bachelors in Electronics and TelecommunicationsEngineering from the University of Mumbai, India. He can be reached at .

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