Optimization and signal-processing algorithm exploration technology lowers power and ASIC die size while maintaining high-performance digital filters, NCOs, and modulators.
GATeIC now offers ASIC designers significant power and area savings for madeto-spec digital data path blocks such as filters, NCOs, and modulators. The company's SoftGATe spec-to-GDSII automation platform, optimized for Synopsys' Galaxy Implementation Platform, lets designers automate the creation and optimization of implementation-ready custom IP for ASICs within days of settling on specifications.
In time critical ASIC projects, designing a single instance of a DSP chain comprised of digital filters, NCOs, modulators, and other digital blocks can consume months of engineering resources. GATeIC's SoftGATe automation platform, combined with Synopsys' Galaxy Platform, reduces this time from months to days, while enabling optimizations for power, area, and performance at the block and system levels.
A key feature of SoftGATe is its automated capability to generate a rich design space of bit-accurate implementations for a given set of specifications, configure the corresponding HDL code, and implement all designs using Synopsys Design Compiler synthesis on the Galaxy Platform. SoftGATe generates input for Synopsys' IC Compiler physical implementation tool, the Star-RCXT parasitic extraction tool, and the PrimeTime PX power analysis solution to generate fully placed, routed GDSII, and extracted power for IP exploration and trade-off analysis. Running all bit-accurate designs through the Galaxy Platform in parallel minimizes time-to-optimized-design, by creating implementations that strike the desired balance between area, power, performance and other specs, to optimize manufacturing cost per unit of power saved.
For more information, go to www.gate-ic.com.