Guidelines for designing an M-LVDS clock distribution network - Embedded.com

Guidelines for designing an M-LVDS clock distribution network

Many telecom systems, including those designed based on the AdvancedTCAarchitecture specifications, require synchronization of their internalinterfaces and the external networks. To enable implementation of suchsystems, the AdvancedTCA or PICMG 3.0specification defines asynchronization clock interfacein the architecture.

Per this specification, the task of sourcing clock signals has beenassigned to ICs conforming to TIA/EIA-899(Multipoint LVDS or M-LVDS)standard.

In an AdvancedTCA backplane, there are three connector zones: zone 1for power connection and shelf management; zone 2 for data transportinterfaces; and zone 3 for user-defined I/O interconnect (Figure 1, below ).

Figure1: With AdvancedTCA, each slot can have up to five ADF or zone 2connectors.

The data transport interfaces are base, fabric, update channel andsynchronization clock interfaces. These interfaces provide connectivitybetween up to 16 slots. Each slot can have up to five advanceddifferential fabric (ADF) or zone 2 connectors (Figure 1, above ). Examples of theADF connectors are Tyco HM-Zd and ERNI ERmetZD.

The clock synchronization interface enables exchange of timinginformation between all slots in the backplane. It consists of threepairs of redundant clock buses: CLK1A, CLK1B, CLK2A, CLK2B, CLK3A andCLK3B. The PICMG 3.0 specification defines usage, frequency and qualityof each clock group:

CLK1A and CLK1B are for redundant 8kHz standard digital telephonytransmission system clocks.

CLK2A and CLK2B are for 19.44MHz clocks for synchronization of theSONET/synchronous digital hierarchy networks.

CLK3A and CLK3B are for user-defined signals (clock or data).

Figure2: M-LVDS drivers and receivers create a multipoint clock distributionnetwork when three or more line cards are installed in the backplane.

The first two rows of pins of each P20 ADF connector connect to thesix clock buses. The buses are essentially 130 ohms differential PCBtraces terminated with 80 ohms resistors on both sides. Figure 2, above shows how M-LVDSdrivers and receivers create a multipoint clock distribution networkwhen three or more line cards are installed in the backplane (Figure 3 below ).

Figure3: Each line card can be set up as a driver or receiver card (all sixdevices on the card configured as M-LVDS receivers).

Dealing with the M-LVDS standard
The M-LVDS (TIA/EIA-899) Standard specifies the electricalcharacteristics of line drivers and receivers intended for general datatransport within a multipoint bus, where up to 32 nodes may beconnected. More specifically, it defines driver output characteristicsand input characteristics of two receiver types.

Table1: LVDS is a popular interface for point-to-point topologies. The keyM-LVDS receiver specifications are input voltage threshold and inputcommon mode range.

Per the TIA/EIA-899 standard, the M-LVDS driver generates adifferentialsignal with 480-650mV amplitude and an offset within the 0.3-2.1Vrange. The signal must have 10-90 percent transition times of 1ns orgreater and up to one-half of a unit interval (t ui )to alleviate theeffects of stubs that are the “artifacts” of multipoint architectures. Table 1 above summarizes keycharacteristics of LVDS (popular interface for point-to-pointtopologies) and M-LVDS drivers.

Figure4a: Type 1 receivers have threshold levels centered at 0V and providehigher noise margin than type 2 receivers.

The key M-LVDS receiver specifications are input voltage thresholdand input common-mode range. The input threshold levels differentiatethe two types of MLVDS receivers. Type 1 receivers (Figure 4a, above ) have thresholdlevels centered at 0V and provide higher noise margin than type 2receivers. These have lower positive noise margin but provide fail-safeprovisions for control signals (Figure4b, below ).

Figure4b: Type 2 receivers have lower positive noise margin but providefailsafe provisions for control signals.

The receiver input common mode range of -1.4-3.8V makes M-LVDS arobust interface for connecting subsystems that may have potentialdifference between their ground references of up to ±1V.

(Currently, National's family ofM-LVDS devices consists of foursingle-channel devices: DS91D176, a half duplex with type 1 M-LVDSinputs; DS91C176, a half duplex with type 2 M-LVDS inputs; DS91D180, afull duplex with type 1 M-LVDS inputs; and DS91C180, a full duplex withtype 2 M-LVDS inputs. This article further reports the performance ofthe DS91D176, a representative of the family, in an AdvancedTCAbackplane .)

Good vs. marginal
A 14-slot dual-star AdvancedTCA compliant backplane and 14 line cards(P/N: DS91D176EVK) enabled testing of various multipoint clockdistribution networks. Each line card features six DS91D176 deviceswhose M-LVDS I/O pins connect to an ADF connector.

By installing the line card in the backplane, each of the sixdevices on the card connects to each of the six clock buses on thebackplane. Installation of all 14 line cards creates six multidropnetworks. Each line card can be set up as a driver card (all sixdevices configured as M-LVDS drivers) or a receiver card (all sixdevices on the card configured as M-LVDS receivers)(Figure 3, earlier ).

Table2: The stub lengths range from 0.25- 2inches, and differential stubimpedances range from 80-130 ohms.

On the M-LVDS line card, the unterminated short PCB tracks (stubs)that connect M-LVDS I/O pins to the bus have different geometries foreach device. The stub lengths range from 0.635-5.08 centimeters, anddifferential stub impedances range from 80-130 ohms (Table 2, above). Thecharacteristics of the stubs foundon the line card are show in Table 3below .

Table3: Noise margin depends on driver and receiver cards locations and stublength.

Regarding the performance of M-LVDS clock distribution networks,noise margin differentiates a good design from a marginal one. Stubsare the major detriment to noise margin in a multidrop environment (Table 4, below ). They reduce noisemargin in two ways.

Table4: Noise margin is higher with shorter stubs.

First, stubs load the bus, and as a result, reduce the amplitude ofthe driver output signal. Second, stubs create impedancediscontinuities that cause reflections, further reducing availablenoise margin (Table 5, below ).In this experiment, the evaluation method consists of looking at theavailable noise at the input of each receiver, and examining effects ofclock driver position and stub characteristics on the noise margin.

Table5: Higher-impedance stubs have a lesser impact on noise margin.

Findings, results
Extensive experimentation with various multidropconfigurations , stub lengths, stub impedances and frequencies has led to the following set ofconclusions:

Noise margin on thereceivers' inputs is higher if the location of the driver card iscloser to one of the termination resistors. In other words, the firstand the last slot in a backplane are the best driver card locations;slots in the middle are the worst.

Noise margin is the lowest for the receivers in the slot adjacentto the slot with the driver card—it is the highest for the receivers onthe furthest card. Table 2 earlier shows available noise margin for thereceivers in the slot adjacent to and furthest from the slot with thedriver card. The backplane is fully loaded and the clock frequency is19.44MHz.

Noise margin is higher with shorter and narrower stubs (Table 2 earlier ). Once a stub startsto behave as an unterminated transmission line, at the point where itconnects to the bus, it lowers the impedance of that section of thebus. These impedance variations or discontinuities along the bus causereflections that lower noise margin.

Figure 5 below shows effectsof the stub length on the available noise margin for the receivers inslot #8 while the driver card is in slot #7 and driving a 19.44MHzclock to all 13 receiver cards.

Figure5: Once a stub starts to behave as an un-terminated transmission line,at the point where it connects to the bus, it lowers the impedance ofthat section of the bus.

In Figure 5, above , thefour waveforms are measured at the input of the adjacent receivers fromthe four networks with 0.25-, 0.5-, 1- and 2-inch stubs. It is clearthat the receiver from the network with 2-inch stubs has the lowestnoise margin.

Table 4 earlier presentsmeasured noise margin for the receivers in slot #8, while the drivercard is in slot #7 and driving clock signals to all 13 receiver cardsat some common frequencies.

At 100MHz, the maximum frequency allowed for AdvancedTCA systems,signals have the most attenuation and become sine-wave-shaped waveformswithout any major reflections at the receiver. As a result, noisemargin is the highest at that frequency.

Figure6: The receiver from the network with 130 ohm stubs has the highestnoise margin.

Figure 6, above showseffects of the stub impedance on the available noise margin for thereceivers in slot #8 when the driver card is in slot #7 and drives a19.44MHz clock to all 13 receiver cards. The three waveforms aremeasured at the input of the adjacent receivers from the three networkswith 80, 100 and 130 ohm stubs. The receiver from the network with 130ohm stubs has the highest noise margin.

Table 5 earlier showsmeasured noise margin for the receivers in slot #8 when the driver cardis in slot #7 and drives clock signals to all 13 receiver cards at somecommon frequencies.

Tips and Tricks
Designing an AdvancedTCA-compliant M-LVDS clock distribution network isa not as straightforward a task as it seems if one only relies on therecommendations given in the PCIMG 3.0 standard.

The following set of design recommendations and tips derived fromexperimentation with an AdvancedTCA-compliant backplane can help builda reliable clock distribution network with the highest noise marginpossible:

Select M-LVDS drivers with the slowest transition time that willsatisfy the bandwidth requirements of your clock system. TIA/EIA-899standard specifies 1ns as the minimum transition time for output of anM-LVDS driver. In an AdvancedTCA backplane with 1-inch stubs, 1nstransition time is too fast for certain configurations. M-LVDS driversfrom National Semiconductor have typical 10-90 percent transition timesof 1.7ns and can operate at frequencies of up to 100MHz.

Place your clock drivers on line cards located in slots closer tothe ends of the backplane provided other system requirements allow it.This arrangement creates longer signal paths. The longer signal pathsare lossier and lay down the signal edges. Again, slower transitiontimes are more “forgiving” when they encounter impedancediscontinuities.

Minimize the stub length as much as possible. The PCIMG 3.0specifies 1inch (excluding the ADF connector) as the maximum stublength for M-LVDS devices. Anything longer than that may cause yoursystem to fail. Shortening the stubs from 1inch to half inch mayincrease your noise margin by 50 percent.

When noise margin is at a premium, one should consider maximizingthe stub impedance. This can be accomplished by either increasing thedielectric thickness between the stub and the copper planes or bymaking the stubs as narrow as PCB manufacturers can make it (inaddition to minimizing the stub length) or both.

Any power supply noise can reduce available noise margin. Ensurethat M-LVDS devices are properly decoupled. Use two vias for VDD andGND pins, and place decoupling capacitors close to the device VDD pin.

Short, narrow stubs coupled with signal drivers (i.e. M-LVDS linedrivers) that have controlled output edge rates are the key toincreased noise margin and improved overall performance of anymultipoint network. By keeping this in mind and following PCB designrecommendations, reliable clock distribution networks can be designedwith ease.

Davor Glisic is SeniorApplications Engineer at NationalSemiconductor Corp. 

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.