HCI and NBTI Reliability Impact on Submicron IC Design - Embedded.com

HCI and NBTI Reliability Impact on Submicron IC Design

Reliability-related IC issues have existed for decades as many papers presented at the IRPS (International Reliability Process Symposium) Conferences for many years can attest. However, until now, HCI (Hot Carrier Injection) and NBTI (Negative-Bias Thermal Instability) issues have not had a significant enough impact on designs due to the larger geometry IC processes of days past. For designs that are now using 0.13 micron or below processes, some design teams have been finding out the hard way that they should have done HCI and NBTI analyses to ensure they can deliver maximum performance chips. Additionally, since these IC processes will become mainstream in 2002, NBTI reliability analysis has become a key issue for designers to address. However, designers currently doing high-performance designs or those with high-reliability requirements will need to address these issues now. Identifying reliability-related performance problems earlier in design process means faster and more reliable end products with vastly reduced chip re-spins, wasted silicon, and potentially millions of dollars spent on mask tooling and problematic first silicon.

Who Should be Concerned About Reliability-Related Degradation?
HCI and NBTI reliability issues must be addressed by any designer who is pushing for highest performance ICs with 0.13 micron or below process technologies that use thermal nitrides for the gate insulator. This specifically includes foundries, Integrated Device Manufacturers (IDMs), and fabless houses having control over their IC processes. Additionally, fabless design companies”even those using standard libraries in an effort to maximize performance of their high-end ASIC or SoC”will need to address reliability-induced degradation. For fabless designers using standard libraries, designers will need to work together with their foundry resource in establishing library data and software that can work with this data to address reliability-induced problems.

Performance More than Reliability
HCI- and NBTI-related problems are performance problems more than failure or “reliability” problems. The traditional “DC Stress” tests now result in such short DC lifetimes that designers can no longer trust these DC tests as a true measure of realistic AC lifetimes. Without quantifiable reliability-design solutions in place, designers will either sacrifice performance due to “over margining” for artificially pessimistic corner cases or they will have excessive burn-in failures”all very late in the design process. Certainly, for those with critical reliability needs, such as implanted medical, aerospace, or other safety-critical applications, reliability is a key concern for avoiding in-the-field failures. However, the most significant impacts caused by reliability issues are reduced design performance, design delays, chip re-spin costs and lost time-to-market. Numerous studies have proven how much more value an IC can warrant in the market by having extra performance in those devices sold to the market earlier rather than later.

About HCI-Induced Degradation
HCI degradation slows down circuit speeds, potentially cause circuit-operating failures (Figure 1 ). HCI arises as a result of the aggressive scaling of device geometries, most notably for short-device channel lengths. Shorter channel lengths mean higher circuit speeds, but they also increase electric fields in the channel. These fields can damage the gate-oxide interface, resulting in degradation in device performance. The amount of device degradation is not constant for each device, but is a function of the device's unique switching activity within each circuit. In the past, designers had no means of uncovering such specific information.

Figure 1: A simulation in Cadence's Analog Artist shows HCI-induced transistor-switching degradation

About NBTI
NBTI degradation is critical for chip processes using thermal-nitride gate insulators”which are now at such thicknesses that NBTI effects can prevent a chip designer from relying on the expected performance of the process. Unlike HCI, NBTI is not exclusively for short-channel devices, since it is directly related to process shrinks in the vertical geometries (Figure 2 ). Like HCI, the amount of device degradation is not constant for each device, but is a function of the device's unique switching activity within each circuit. Additionally, for devices that are subject to high-temperature conditions, whether due to the chip's own heat dissipation or the environment in which the chip will be used, NBTI failures will occur in the field independent of those found during burn-in testing. In the past, designers had no means of uncovering such specific information other than using artificial DC stress tests and reduced yield from high-temperature burn-in failures, or by designing all parts of the chip to absolute worst-case corner conditions. An NBTI design solution will help a designer identify where problems might exist so the designer can design around situations such as voltage overshoot, as well as other conditions for which a designer can compensate without sacrificing performance.

Figure 2: This graph shows how transistor threshold-voltage changes over time due to NBTI effects

Designing without Reliability Design Solutions
Without any reliability modeling or simulation, a designer is forced to resort to an overly conservative design style, (known as guard-banding) which, in turn, reduces chip performance as well as running the risk of early chip failures in the field. Also, by doing more complete reliability assessments, a designer can avoid problems that, in the past, may only have been found during chip burn-in. Avoiding a problem earlier is extremely valuable, considering the chip tooling costs to do a re-spin and the time to market impacts of finding problems so much later in the design cycle.

About the Authors
Mr. Dale Pollek, Vice President of marketing at Celestry Design Technologies, has over 20 years of experience in EDA and EDA-user community. He received his BSEE from University of Wisconsin, with a focus in device physics and IC characterization.

Dr. Xiaolan Wu, Director of Technical Marketing at Celestry, has spent her career engaged in research in the areas of CMOS and BiCMOS process integration, test-chip design, device and interconnect modeling, and critical design-path timing verification. She received her Ph.D. in electrical engineering from the University of Minnesota.

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