High channel density distinguishes digital downconverter core for FPGAs - Embedded.com

High channel density distinguishes digital downconverter core for FPGAs

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Upper Saddle River, N.J.—The Model 4954-430, an addition to Pentek Inc.'s GateFlow FPGA intellectual property (IP) core library, puts a narrowband digital downconverter onto Xilinx Virtex II, Virtex II Pro, or Virtex-4 FPGAs. The core's 256 channels are 64 times the number available on conventional quad counterparts.

The core accepts 16-bit real or complex data samples at rates up to 185 MHz and generates 256 independently tunable 16-bit complex outputs ranging in output bandwith from about 14.8 to 144 kHz. The core includes a channelizer stage that generates 1,024 fixed adjacent frequency channels, each alias-free and separated by 75 dB of stopband attenuation.

A 256-output channel switch matrix follows the channelizer to offer course tuning to the desired output channel. For fine tuning, each of the 256 digital downconverters has a 32-bit numerically controlled oscillator, as well as a mixer to extract baseband signals.

In addition, a decimating FIR low-pass filter defines the channel bandwidth of the baseband output. Each baseband output goes through an independently programmable gain stage before being rounded to its final 16-bit result.

The decimation factor setting, common to all channels, resides in RAM and is user programmable from 1,024 to 9,984 in steps of 256. Alternatively, a complete set of 35 factory default values for decimation factors is supplied for an 80-percent passband filter response.

The Model 4954-430 sells for $14,995 with a delivery time of eight to 10 weeks ARO. Pentek's GateFlow IP library cores are offered under the company's SignOnce IP project license, the industry's first multivendor common license for FPGA-based IP. Cores are also available as a factory-installed option on appropriate Pentek FPGA boards.

Pentek, Inc. , 1-201-818-5900, www.pentek.com

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