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# High frequency synchronizer design with programmable mean-time-between-failure capabilities

This article describes a high frequency synchronizer circuit with programmable mean-time-between-failure (MTBF) cababilities that is well suited for high frequency clock gating and input signal synchronization applications.

Synchronizer circuits are commonly used in modern System on Chip (SoC) designs to facilitate the reliable data transfer between independent clock domains [1, 2]. As design geometry shrinks and clock speeds approach the gigahertz range, the design of synchronizer circuits becomes a challenging task. Metastability (the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state) is a key factor to be considered. The MTBF (mean time between failures) value, which is a figure of merit related to metastability, degrades sharply when input clock and/or data frequency is increased, as per the synchronizer MTBF formula given in this equation:

In the equation, Fclk and Fdata are input clock and data frequency respectively, tMETA is the time delay allowed for metastability to resolve itself, C1 is a constant representing the metastability catching setup time window and C2 is a constant describing the speed with which the metastable condition is resolved.

The possible ways to increase MTBF are by cascading more flip-flops in the synchronizer circuit or by running the synchronizer at a slower frequency. In both the cases, tMETA value increases and the MTBF value increases exponentially as per equation (1). The proposed synchronizer enhances the MTBF value by dividing the high frequency input clock by a user defined division ratio, N.

With a standard two flip-flop synchronizer, the delay introduced between the input and the synchronized output is equal to one flip-flop’s clock-to-output delay (Tcàq) plus the delay of an AND gate (Tand). To increase the MTBF, if a standard two flip-flop synchronizer is run with a divided clock, the total delay between the input and the synchronized output will become 2*Tcàq + Tand. The additional Tcàq delay is contributed by the clock divider circuit. Due to this extra Tcàq delay of a flip-flop, a glitch may appear in the synchronized output if the total delay is more than the OFF period of the input clock.

The situation will further degrade if the input clock duty cycle is more than 50%, further reducing the OFF period of the input clock. In the proposed synchronizer, instead of an extra Tcàq delay contributed by the clock divider circuit, only a NAND gate delay (Tnand) is added, which is much less as compared to Tcàq. The typical values of Tcàq and Tnand are approximately 300ps and 30ps respectively in 90nm CMOS technology. Thus, the total delay becomes Tcàq + Tand + Tnand and the proposed synchronizer is able to run at a much higher frequency as compared to a standard two flip-flop synchronizer.

Circuit Description
Figure 1 shows the block diagram of the proposed synchronizer. The asynchronous input data is captured by the input flip-flop (FF). The output of the input FF is captured by a standard two flip-flop synchronizer, running on a divided input clock.

Figure 1: Block diagram of the proposed synchronizer

Figure 2 shows the circuit diagram of the proposed synchronizer. The input clock, clk, goes to a divide by 4 circuit (N=2) composed of flip-flops FF4 and FF5. This divider can be made programmable to divide by N=2, 3, 4 etc. The flip-flops FF2 and FF3 form a standard two flip-flop synchronizer which is driven by the rising edges of the generated clock, clk_gated. The frequency of clk_gated is equal to one-fourth of the frequency of clk.

Figure 2: Circuit diagram of the proposed synchronizer

As shown in Figure 2, the delay between clk and clk_gated is equal to the delay of a NAND gate, NAND1. The overall MTBF of the synchronizer will be the MTBF of FF1 (MTBF1) times the MTBF of the synchronizer composed of FF2 and FF3 (MTBF2).

Because clk and data are asynchronous, FF1 can enter into a metastable state whenever a transition at its data input – with respect to a transition at its clock input – happens in the setup-hold window, which is typically 100ps-150ps. Similarly, FF2 can enter into a metastable state whenever a transition at data_mid1 with respect to a transition at clk_gated happens in the setup-hold window.

It is clear from Figure 2 that even if FF2 output, data_mid2, becomes metastable, the time it will get to resolve the metastable state will be four times the time period of clk. Also, since the frequency of clk_gated is one-fourth of clk, the overall MTBF improvement will be 4e4 (~218.4) times as compared to a standard two flip-flop synchronizer. Qualitatively, because of quadruple increase in tMETA, probability of FF3 going into metastable state decreases significantly. In general, dividing the input clock by N improves the overall MTBF by NeN. However, an increase in N also increases the number of clk cycles required before the synchronized output, data_sync, appears. The number of clk cycles required depends upon relative timing of data transition at data and data_mid1 with respect to clk and clk_gated respectively, and
whether FF1 and/or FF2 entered into a metastable state.

For applications where this additional latency is immaterial, MTBF can be increased at the expanse of latency, with only marginal increase in the delay between the clk and the synchronized output. Typically, MTBF is designed to be at least ten times the expected lifetime of the product.

The different scenarios of flip-flops entering into metastable states and the maximum number of clk cycles required for valid synchronized output for different scenarios are shown in Figure 3 in the form of a flow chart. Just like a standard two flip-flop synchronizer, the proposed synchronizer can be defined as a synthesizable IP that can be readily used in an SoC environment.

Figure 3: Flow chart for the proposed synchronizer

Simulation Results
The proposed synchronizer has been designed in CMOS90 technology with clk frequency equal to 2GHz. Figure 4  shows the generation of divided by 4 clock, clk_gated. The other simulated waveforms are also shown, which correspond to the circuit nodes shown in Figure 2. It is clear fromFigure 4that the periods of clk and clk_gated are 500ps and 2ns respectively.

Figure 4:  Simulation waveforms showing generation of clk_gated clock

For a case in which the data does not fall in the setup-hold window of the clk, the output of FF1 will not be in a metastable state and the synchronized output will occur between 5 and 8 clk cycles. When the data falls in the setup-hold window of the clk, the output of FF1 becomes metastable. This situation gives rise to two sub-cases

(i) first edge of the clk_gated coincides with second clk edge.
(ii) first edge of the clk_gated coincides with 3rd, 4th or 5th clk edge.

In sub-case 1, FF2 captures the metastable data at second clk edge. However, the time available to FF2 to resolve its metastable state has been increased to four times (= 4/fclk). If after the four clk cycles, data_mid2 settles to its correct logical value, FF3 will capture the correct data at 6th edge of clk. On the other hand, if after the four clk cycles, data_mid2 resolves its metastable state in an undesired logical value, FF3 will capture the correct data at 10th edge of clk. For sub-case 2, the output of FF1 comes out of metastable state at the second clk edge before it is captured by FF2. FF2 captures the correct data at 3rd, 4th or 5th clk edge and FF3 captures the correct data at 7rd, 8th or 9th clk edge respectively.

Figure 5  shows the simulation result of clk_out generation. This is an example of clock gating scenario where clk_out starts coming in response to a low-to-high transition in data. There is no glitch in the first cycle of clk_out because of a synchronized start. This result shows a data signal synchronized with a 2GHz clock.

Figure 5:  Simulation waveforms showing generation of clk_out clock

Conclusion
In this fully parameterized, gigahertz-range synchronizer circuit designed to provide NeN times increase in MTBF value as compared to a standard two flip-flop synchronizer, the division factor N is user programmable and provides a trade-off between synchronized output latency and MTBF value. A larger value of N provides higher MTBF but at the cost of additional latency. As compared to a standard two flip-flop synchronizer, the proposed synchronizer introduces an extra NAND gate delay in the synchronized output which is very much reduced in today’s deep sub-micron CMOS technologies. Simulation results in CMOS90 technology with 2GHz input clock frequency show the expected behavior of the proposed synchronizer.

Sanjay Kumar Wadhwa  received his B. Tech. degree in Electronics and Communication Engineering from National Institute of Technology (NIT), Kurukshetra, India in 1996. Since then, he has worked in the field of analog and mixed signal designs for various applications. He is presently working with Freescale Semiconductor India design centre in the field of PLLs and low power analog circuits. He has published 14 papers in various VLSI conferences, has 4 defensive publications and holds 16 US patents. He has been recognized as a Distinguished Innovator by Freescale Semiconductor. His main interests are in the design of low voltage, low power, and low area, high performance analog and mixed signals circuits.

References
[1] Ran Ginosar, “Fourteen Ways to Fool Your Synchronizer,” Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC03), pp. 89-96.
[2] Chuck Brown and Kamilo Feher, “Measuring Metastability and its Effect on Communication Signal Processing Systems,” IEEE Transactions on Instrumentation and Measurement, vol. 46, pp. 61 – 64, Feb. 1997.

## 1 thought on “High frequency synchronizer design with programmable mean-time-between-failure capabilities”

1. MSA2000 says:

Hi Sanjay,
I am having trouble understanding why you multiply MTBF1 by MTBF2?
Could you please elaborate on that.

Regards,
MSA