High-performance embedded computing - Comparing results - Embedded.com

High-performance embedded computing — Comparing results


Editor's Note: Interest in embedded systems for the Internet of Things often focuses on physical size and power consumption. Yet, the need for tiny systems by no means precludes expectations for greater functionality and higher performance. At the same time, developers need to respond to growing interest in more powerful edge systems able to mind large stables of connected systems while running resource-intensive algorithms for sensor fusion, feedback control, and even machine learning. In this environment and embedded design in general, it's important for developers to understand the nature of embedded systems architectures and methods for extracting their full performance potential. In their book, Embedded Computing for High Performance, the authors offer a detailed look at the hardware and software used to meet growing performance requirements.

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Adapted from Embedded Computing for High Performance, by João Cardoso, José Gabriel Coutinho, Pedro Diniz.

By João Cardoso, José Gabriel Coutinho, and Pedro Diniz

When comparing execution times, power dissipation, and energy consumption, it is common to compare the average (arithmetic mean) results of a number of application runs. This reduces the impact of possible measurement fluctuations as most of times measurements can be influenced by unrelated CPU activities and by the precision of the measuring techniques. Depending on the number of measurements, it might be also important to report standard deviations. When comparing speedups and throughputs, however, it is convenient to compare the geometric mean of the speedups/ throughputs achieved by the optimizations or improvements for each benchmark/ application used in the experiments, as opposed to the use of arithmetic mean for speedups which may lead to wrong conclusions. [Note: How did this get published? Pitfalls in experimental evaluation of computing systems. Talk by Jos e Nelson Amaral, Languages, Compilers, Tools and Theory for Embedded Systems (LCTES’12), June 12, 2012, Beijing.] In most cases, the measurements use real executions in the target platform and take advantage of the existence of hardware timers to measure clock cycles (and correspondent execution time) and of the existence of sensors to measure the current being supplied. Most embedded computing platforms do not include current sensors and it is sometimes needed to use a third- party board that can be attached to the power supply (e.g., by using a shunt resistor between the power supply and the device under measurement).

There are cases where performance evaluations are carried out using cycle- accurate simulators (i.e., simulators that execute at the clock cycle level and thus report accurate latencies) and power/energy models. Cycle-accurate simulations can be very time-consuming and an alternative is to use instruction-level simulators (i.e., simulators that focus on the execution of the instructions but not of the clock cycles being elapsed) and/or performance/power/energy models. Instruction-level simulators are used by most virtual platforms to simulate entire systems, including the presence of operating systems, since they provide faster simulations.

The comparison of results is conducted in many cases using metrics calculated from actual measurements. The most relevant example is the speedup which allows the comparison of performance improvements over a baseline (reference) solution. In the case of multicore and many-core architectures, in addition to the characteristics of the target platform (e.g., memories, CPUs, hardware accelerators) it is common to report the number of cores and the kind of cores used for a specific implementation, the number of threads, and the clock frequencies used.

Regarding the use of FPGAs, it is common to evaluate the number of hardware resources used and the maximum clock frequency achieved by a specific design. These metrics are reported by vendor-specific tools at more than one level of the toolchain, with the highest accuracy provided by the lower levels of the toolchain. Typically, the metrics reported depend on the target FPGA vendor or family of FPGAs. In case of Xilinx FPGAs, the metrics reported include the number of LUTs (distinguishing the ones used as registers, as logic, or as both), slices, DSPs, and BRAMs.


This chapter described the main architectures currently used for high-performance embedded computing and for general purpose computing. The descriptions include multicore and many-core integrated circuits (ICs) and hardware accelerators (e.g., GPUs and FPGAs). We presented aspects to take into account in terms of performance and discussed the impact of offloading computations to hardware accelerators and the use of the roofline model to reveal the potential for performance improvements of an application. Since power dissipation and energy consumption are of paramount importance in embedded systems, even when the primary goal is to provide high performance, we described the major contributing factors for power dissipation and energy consumption, and some techniques to reduce them.


This chapter focused on many topics for which there exists an extensive bibliography. We include in this section some references we believe are appropriate as a starting point for readers interested in learning more about some of the topics covered in this chapter.

Readers interested in the advances of reconfigurable computing and reconfigurable architectures can refer to, e.g., [1,36–38]. An introduction to FPGA architectures is provided in Ref. [2]. The overviews in Refs. [39,40] provide useful information on code transformations and compiler optimizations for reconfigurable architectures in the context of reconfigurable computing. Overlay architectures provide interesting approaches and have attracted the attention of academia as well as of industry (see, e.g., [20,41]).

A useful introduction about GPU computing is presented in Ref. [6]. In addition, there have been several research efforts comparing the performance of GPUs vs FPGAs (see, e.g., [42]).

Computation offloading has been focus of many authors, not only regarding the migration of computations to local hardware accelerators but also to servers and/or HPC platforms. Examples of computation offloading include the migration of computations from mobile devices to servers (see, e.g., [43]).

Exploiting parallelism is critical for enhancing performance. In this context, when improving the performance of an application, [Note that the Amdahl’s law can be also applied to other metrics such as power and energy consumption.] developers should consider Amdahl’s law and its extensions to the multicore era [44,45] to guide code transformations and optimizations, as well as code partitioning and mapping.

There have been many approaches proposed to reduce power and energy consumption using DVFS (see, e.g., [46]). A recent and useful survey about DVFS and DPM is presented in [47]. Readers interested in power-aware computing topics are referred to Ref. [48]. Mobile devices have typically strict power and energy consumption requirements. Thus several approaches have addressed APIs for monitoring power dissipation in mobile devices. An energy consumption model for Android- based smartphones is PowerTutor [49]. Readers interested in self-build energy model approaches can refer to Ref. [50].

While the use of simple performance models is well understood for single-core architectures, further understanding is needed to extend or revisit Amdahl’s law and its main lessons and extensions to the multicore era as addressed by recent research [44,45]. The complexity of emerging architectures with processor heterogeneity and custom processing engines will also likely lead to advances in more sophisticated models such as the roofline model [51,25] briefly described in this chapter. 


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The next installment in this series discusses code retargeting for CPU-based platforms.

Reprinted with permission from Elsevier/Morgan Kaufmann, Copyright © 2017

João Manuel Paiva Cardoso , Associate Professor, Department of Informatics Engineering (DEI), Faculty of Engineering, University of Porto, Portugal. Previously I was Assistant Professor in the Department of Computer Science and Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon (UTL), in Lisbon (April 4, 2006- Sept. 3, 2008), and Assistant Professor (2001-2006) in the Department of Electronics and Informatics Engineering (DEEI), Faculty of Sciences and Technology, at the University of Algarve, and Teaching Assistant in the same university (1993-2001). I have been a senior researcher at INESC-ID (Systems and Computer Engineering Institute) in Lisbon. I was member of INESC-ID from 1994 to 2009.

José Gabriel de Figueiredo Coutinho , Research Associate, Imperial College. He is involved in the EU FP7 HARNESS project to intergrate heterogeneous hardware and network technologies into data centre platforms, to vastly increase performance, reduce energy consumption, and lower cost profiles for important and high-value cloud applications such as real-time business analytics and the geosciences. His research interests include database functionality on heterogeneous systems, cloud computing resource management, and performance-driven mapping strategies.

Pedro C. Diniz received his M.Sc. in Electrical and Computer Engineering from the Technical University in Lisbon, Portugal and his Ph.D. from the University of California, Santa Barbara in Computer Science in 1997. Since 1997 he has been a researcher with the University of Southern California’s Information Sciences Institute (USC/ISI) and an Assistant Professor of Computer Science at the University of Southern California in Los Angeles, California. He has lead and participated in many research projects funded by the U.S. government and the European Union (UE) and has authored or co-authored many internationally recognized scientific journal papers and over 100 international conference papers. Over the years he has been heavily involved in the scientific community in the area of high-performance computing, reconfigurable and field-programmable computing.

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