High-speed bus architectures bring new challenges - Embedded.com

High-speed bus architectures bring new challenges

Tektronix has had to re-think the approach to logic analysis and probe design as in digital systems of all kinds, IC components have led the charge toward higher speeds and functionalities. Within their tightly-controlled silicon structures, many of these devices now operate at cyclic rates in the gigahertz range.

An element such as a CPU or a DSP component needs to exchange millions of cycles' worth of data with other parts of the system in which it resides; this information travels via bus structures from device to device.

While the silicon components have the advantage of microscopic internal path lengths, carefully tailored signal levels and controlled impedances, signals traversing a bus must confront a far less ideal environment: the 'real world'.

For decades, parallel bus architectures have been the most common means of transporting digital signals around a system. In a simplistic parallel bus architecture, a 32bit bus emanating from a CPU has 32 drivers, 32 physical traces, and 32 receivers at the destination device. In a system with many sources and destinations, this would lead to an impossibly complex circuit layout, so most parallel buses are bi-directional. Depending on the state of various enable and timing bits, they carry both outgoing and incoming signals over the same physical connections.

Now that system data rates have accelerated into the gigabits-per-second range, the limitations of conventional parallel bus architectures are beginning to show. Most importantly, the sheer number of signals becomes very cumbersome to synchronize, especially as those signals are randomly affected by factors such as noise and crosstalk. The CPU must wait for all these signal lines – more than a hundred in some cases – to stabilize before clocking in an instruction, which offsets the original benefit of increasing the CPU speed. A large amount of energy is required to transmit data over a wide bus, exacerbating ground bounce and noise problems. Path length and impedance are difficult to control, and a large amount of circuit board real estate is required to situate wide parallel buses. Moreover, the process of switching between sending and receiving on a bi-directional bus takes extra time.

Parallel bus architectures are just one path toward high-speed data transmission. The industry is turning to other bus technologies in an ongoing quest for faster, simpler architectures.

After years of ever-increasing parallel bus widths, an alternative bus technology trend is taking us in the opposite direction. Narrow serialized buses have emerged to take the place of wide parallel architectures. What was once a 128-bit parallel connection might become, for example, a four-line serial bus. A 16- or 32-bit parallel bus might shrink to just one or two lines. These few physical lines must of course carry the same amount data as their parallel counterparts – or more.

With serial bus architecture comes the concept of dedicated, uni-directional, point-to-point connections. A Data Out line from the CPU is always an output; there is no reversal of direction to receive data. A separate line brings data into the device elsewhere. By omitting the switching time between transmit and receive states, serial buses can take full advantage of the processor's capacity.

Serialized buses typically carry packetized data. Packetized transmission is enabled by serial bus technology in the physical layer and is implemented in the protocol layer.

In a serial packetized scheme, a data word is not transmitted as one contiguous entity. Instead, its content is distributed over multiple 'packets' of data which are sent over the serial connection and reconstructed in the receiving device. Packetized data is more adaptable (word length can change dynamically as system activity dictates) and more reliable, with built-in provision for error detection and correction.

The benefits of serial bus design are substantial. Fewer signal lines means fewer paths to lay out, with fewer angles, vias, and terminations. Clearly, it is easier to route four signal lines around a board than 64. The circuit board layout is simpler and less vulnerable to unforeseen interactions among the signal lines. And it is easier to keep the path lengths closely matched, which reduces the time required to align signals before clocking them into the receiving device.

Current and emerging serial bus standards include Serial ATA, an architecture aimed at disk storage applications within PCs; and USB 2.0 a high-speed peripheral interface, and Hypertransport, a point-to-point architecture that provides a high-performance link for embedded applications and scalable multiprocessor systems.

Taking the serialized architecture a step further, a new generation of bus architectures is emerging. Known as 'fabrics', these technologies assemble point-to-point, serialized connections into an integrated fabric of switches and links. Fabrics are made up of nodes joined by multiple redundant paths, ensuring reliability (thanks to redundancy) and supporting easy, cost-effective scalability. Examples of emerging fabric architectures include Infiniband (intended to connect servers to remote storage and network devices) and RapidIO (designed to route data within fast digital subsystems). Like all serialized buses, fabrics were developed specifically to address the need for speed.

Designers face new challenges as they incorporate fast serial bus and fabric technologies into their next-generation systems. Pure logic design is no longer enough. Today's system speeds have side effects that must be understood and accounted for, and many engineers are not used to thinking that way. In the past, digital designers concentrated on timing issues between signals. Now they must consider the parameters of signaling among and within devices.

Designers also face a measurement challenge as they plan their strategies to characterize and troubleshoot these signals.

Just how fast are these signals? Simple math tells us that when data travels over one serial connection instead of eight parallel lines, then the data rate on that one line must be eight times as fast if it is to maintain the same overall data rate. And serial buses are fast: Infiniband brings a 2.5Gb/s data rate, with planned expansion to 6Gb/s. RapidIO is even faster at 10Gb/s.

These numbers signify extremely high clock rates, very brief unit intervals (the amount of time allotted for one bit of data), and fast transition rates (the rise and fall time of the digital pulses that make up the data transmission). Often, these phenomena are best viewed with an oscilloscope, which can capture details of signal edges and aberrations.

The use of packetized data transmission brings another dimension to the troubleshooting challenge. It means that the data content is spread out over time, across packets. A failure at the application level might have its roots in the application software itself, the packetizing protocol, the digital logic, or the bus timing. These digital events are best interpreted with a logic analyzer, which can acquire state information – even packetized data – and display it in a meaningful form.

Frequently, engineers troubleshooting fast serial buses encounter digital problems with origins in the quality – the integrity – of the signals that make up the data. An ideal digital pulse is cohesive in time and amplitude; is free from aberrations and jitter; and has fast, clean transitions. At higher operating speeds it becomes ever more difficult to maintain these ideal signal characteristics. That is why signal integrity is 'suddenly' a problem.

As system clock rates reach 500MHz, 1GHz, and beyond, signal integrity plays a larger and larger role in overall system behavior. And every design detail can affect signal integrity: signal path design, impedances and loading, transmission line effects, termination, and more. Signal integrity validation has become a unique discipline with its own tools and processes.

The first line of defense in most digital troubleshooting work is the logic analyzer (LA). This general-purpose instrument allows users to store, trigger on and view digital signals in many formats.

The LA's timing display shows streams of digital pulses and their relative placement in time. The state display format looks at data with timing determined by a clock signal from the unit under test. State results are often expressed in hexadecimal form. These results can be further interpreted with the help of disassemblers and processor support packages, where the logic analyzer can equate high level instructions with low level binary activity.

The current state of the art in logic analyzers addresses these needs with 8GHz acquisition (125 ps timing resolution), configurable channel count into the thousands, up to 256M memory depth, connectorless high-density compression probing, and more. There is advanced analysis software packages to help users derive and interpret high-level code from the acquired binary data. This latter feature is of course indispensable when analyzing packetized serial data.

Many digital problems are best understood by looking at the analog representation of the flawed digital signal. Although the problem may appear as a misplaced digital pulse, the cause of the problem signal could be related to its analog characteristics. Analog characteristics can become digital faults when low-amplitude signals turn into incorrect logic states, or when slow rise times cause pulses to shift in time, and so on.

The digital storage oscilloscope (DSO) can capture the details of individual cycles of digital operations-all the way down to a single pulse or edge. And the DSO can acquire one-time ('single-shot') events that elude other acquisition tools. Especially in a high-speed signal environment, the DSO is the right tool to detect problems such as transients and jitter.

An important aspect of oscilloscope-based signal integrity measurements is the concept of mask testing. In a mask test, the object is to ascertain that the serial signal stays within specified boundaries of time and amplitude. Instead of looking at individual pulses, though the mask test looks at a continuous flow of serialized data. The resulting pattern on the oscilloscope screen resembles an eye, with both positive- and negative-going signal edges displayed at once. Masks delineate the boundaries of this eye. Long a standard in high-speed communications testing, the mask test is an efficient tool for detecting signals with problems in their transition time, duration, or amplitude.

Today's top oscilloscopes meet these requirements with features that include up to 6GHz bandwidth at full sample rate on multiple acquisition channels, record length of up to 32M, low-capacitance movable probes, and a broad range of automation, analysis, and compliance measurement software.

The LA and the DSO are two powerful tools in the signal integrity troubleshooter's kit. But with recent advancements in integration, the power of the two individual tools has been multiplied.

Integrated viewing tools make it possible to connect a DSO (that meets the analog bandwidth needs of the target technology) to a logic analyzer (with adequate channel count, memory depth, and sample rate) to handle the analog and digital measurement requirements. The logic analyzer screen presents digital information as well as the oscilloscope's analog waveform.

The two traces are time-aligned so that the digital event can be examined in its analog form. An error – for example an unexpected extra pulse in the digital waveform – might be seen on the oscilloscope trace as a large aberration in the rising edge of a signal. This analog signal aberration may be either the cause or the effect of an error in the logic within the device under test. But in either case, seeing the underlying analog characteristics helps the designer more quickly track down problems.

There is one other characteristic of both serial and parallel architectures that requires special attention even before measurements begin. Modern circuit board layout and component design have made the all-important bus signals harder to get at; in some cases, they are completely inaccessible. Technologies such as buried vias (on the circuit board) and ball grid array components offer no 'hooks' for logic analyzers and oscilloscopes.

Meeting these challenges requires some preparation in advance. Most importantly, it is necessary to design in test points for the instrumentation. Usually this involves installing a Mictor connector for the logic analyzer and dedicated pads for oscilloscope probing. But now the paired logic analyzer/oscilloscope toolset carries the integrated instruments' capabilities all the way to the test point.

Published in Embedded Systems (Europe) April 2002

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