Hot circuit designs to come at ISSCC 2015 in February - Embedded.com

Hot circuit designs to come at ISSCC 2015 in February

SAN JOSE, Calif. — Chip designs that enable everything from a 6 Gbit/s smartphone interface to the world’s smallest SRAM cell will be described at the International Solid State Circuits Conference (ISSCC) in February.

Intel will describe a Xeon processor packing 5.56 billion transistors, and AMD will disclose an integrated processor sporting a new x86 core, according to a just-released preview of the event.

The annual ISSCC covers the waterfront of chip designs that enable faster speeds, longer battery life, more performance, more memory, and interesting new capabilities.

Several chips now pack more than 5 billion transistors, ISSCC organizers say.

Several chips now pack more than 5 billion transistors, ISSCC organizers say.

The dozens of papers at this year’s event include a handful describing the first designs made in 16 and 14 nm FinFET processes at IBM, Samsung, and TSMC.

Among the novel papers, researchers at the Korea Advanced Institute of Science and Technology stacked an image sensor that tracks eye movements on an object-recognition processor. The device processes 151.3 GOPS at 2.71 nJ/pixel and show the way to natural interfaces for wearable devices.

NHK Science & Technology Research Laboratories and Forza Silicon will show a 12 bit, 133 Mpixel image sensor that delivers 8K video at 60 frames/second. At the other end of the imaging spectrum, Samsung will present a 640×480 pixel image sensor that consumes just 45.5 microwatts at 15 frames/s so it can be used in an always-on mode.

A handful of devices deliver new medical capabilities. For example, researchers in the Netherlands and Switzerland teamed up to design a solid-state endoscopic scanner that promises better image quality using lower radiation doses and at less cost than today’s systems used to detect cancer. Researchers in Japan developed an armband that runs off ambient room light, setting off an alarm if a patient’s temperature exceeds a set limit.

Promising faster communications, Keio University will describe a 6 Gbit/s wireless link for smartphone across a 5 mm distance using a 65 nm chip that consumes 6 picojoules per bit. Researchers from Belgium will show a low-cost plastic waveguide carrying a 100 GHz signal to deliver 12.7 Gbit/s at 1.8 pJ/bit, which could find use in future server racks and cars.

For its part, Intel will describe a SerDes transmitter that carries data up to 40 Gbit/s using a combination of NRZ and PAM-4 modulation schemes. The chip, made in Intel’s 14 nm process, is one of a handful of devices to be described at ISSCC made in emerging FinFET prcesses.

To read more of this external content, go to “ISSCC Tips Hot Circuit Designs.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.