How FPGA technology is evolving to meet new mid-range system requirements -

How FPGA technology is evolving to meet new mid-range system requirements


Multiple trends are sending FPGAs down two distinct development paths.  On one path, FPGAs are being optimized primarily to accelerate data center workloads.  The data center focus is the next holy grail that the larger vendors are laser-focused on.  On another development path, there are the traditional FPGA markets of networking, cellular infrastructure, defense, commercial aviation, industry 4.0 and medical.  In these markets many engineers feel they are being abandoned.  Their development challenges are quite different than the data center focus that the large vendors are focusing on.  Here, designers face an increasingly difficult balancing act as they try to achieve a combination of low power and cost without sacrificing performance and security. Navigating this balancing act requires looking at FPGAs in a new way, using new process technology choices, fabric designs, transceiver strategies and built-in security measures. This has led to a new class of mid-range FPGAs that deliver new capabilities for traditional FPGA developers to leverage.

New Process Technology Choices

One way to reduce power while optimizing the cost of mid-range FPGAs is through the use of new process technologies.  For example, using Silicon-Oxide-Nitride-Silicon (SONOS) non-volatile (NV) technology on a 28nm technology node provides a lower power advantage as compared to both SRAM-based FPGAs at the same or even smaller nodes.  Previous-generation non-volatile FPGAs using 65nm-and-older floating gate NV technology are more expensive than SONOS. Whereas floating gate technology requires 17.5 V to program using large charge pumps that consume a substantial die area, SONOS technology requires only 7.5 V for programming, so charge pumps can be smaller. This technology enables a smaller die size and contributes to a more cost-effective device.

SONOS technology delivers these benefits by using a single poly transistor stack with a non-conductive Nitride dielectric layer (silicon-nitride, Si3N4) as the charge storage element (see Figure 1). Using this approach, only a very small amount of charge will be lost in proximity to any defect that may exist in the bottom oxide. Because the stored charge is non-mobile in the insulating Nitride layer, most of the stored charge remains where it is, intact. A thinner bottom oxide can be used compared to the floating gate technology, and it can be programmed with lower programming voltages (~7.5 V) and smaller charge pumps. Fewer transistors are required with SONOS than with an SRAM memory element.

Figure 1: SONOS technology. (Source: Microsemi)

SONOS technology improves reliability thanks to its use of a push-pull cell containing an N-channel and a P-channel NV device. The NV devices are not in the data-speed path and are only used to control a standard transistor used as the data-path switch. This provides a large functional advantage because any variation in the NV device threshold voltage (Vt) does not change the switch conductance.  The way the devices interact acts as a built-in quasi redundancy, preventing performance degradation over the life of the product.

Power consumption is also reduced.  First, the SONOS NV FPGA configuration cell enables two different programmable “configuration” states that control the FPGA data signal path, switching it off and on in a way that optimizes the switch device to provide much lower leakage than a standard transistor. Second, SONOS technology can put a device into a state that turns the supply voltage off to the configuration memories in the FPGA logic block while saving the user’s state in low-power latches.  This lowers standby power by approximately two-thirds.

There are two other important SONOS benefits.  The first is “instant on” capabilities:  because the FPGA logic configuration cell retains its state after power-down, there is no need to reload the FPGA design code when power is returned, and no need for an external boot PROM. Second, unlike the configuration memory in SRAM-based FPGAs that can flip state due to neutron hits, a SONOS device’s FPGA logic configuration is SEU-immune. The SONOS NV charge is stored in the nitride dielectric, which is not susceptible to charge loss from neutron hits.

New Fabric Designs

Another way to improve mid-range FPGA performance is through changes to the programmable logic fabric.  This enables devices to meet mainstream performance requirements while consuming one-tenth the static power of competing SRAM FPGAs, and half the total power.

Power and performance trade-offs are involved.  As an example, 6-input LUTs can provide some speed benefits, but 4-input LUTs are the better choice for a power- and cost-optimized FPGA in a modern process technology. Meanwhile, as process technology has progressed from 65nm to 28nm and beyond, the delay of wiring has come to dominate logic delay, due to poor scaling of metal wire and via resistance. Widening the wires adds to the die area and cost. So, with each succeeding generation of process technology, inter-cluster delay becomes a significant contributor to the critical path, and the speed advantage of 6-input LUTs diminishes.  Ensuring rapid direct connections between nearby LUTs can reduce intra-cluster delay, especially in conjunction with advanced synthesis and placement algorithms. Certain logic functions (such as MUX trees) greatly benefit from the direct connections.

For best results, an FPGA family’s power-performance tradeoffs should be carefully optimized for a core logic supply voltage that is somewhat less than the nominal voltage for the process on which it is manufactured. In the case of 28nm SONOS devices this means optimizing the family for a 1.0V core logic supply voltage, with the option to use the full 1.05 V supply when extra speed is required.

The final piece of the FPGA fabric is the math block, which should support 18-bit multiply-accumulate operations. Power savings are realized through the provision of a pre-adder with a full 19-bit result and an input value cascade chain, and by ensuring that the math block supports reduced precision 9-bit operations, including 9 × 9 dot-product mode. The latter is ideal for use in image processing and convolutional neural networks (CNNs).

FPGA Transceivers

Transceivers play a major role in optimizing FPGAs for challenging cost, power and performance requirements.  Many applications need up to 24 high-speed full-duplex transceiver channels.  They also need SerDes transceivers that can support baud rates from 250 Mbps to 12.7 Gbps to cover the full range of SDI, Ethernet up to 10Gbps, JESD204B converters and other applications. One primary advantage of optimizing transceivers for this range over downgrading a higher-speed SerDes adapted from a high-end FPGA is that it has significantly lower power at all baud rates compared to a downgraded SerDes approach.

Numerous architectural decisions contribute to cutting FPGA transceiver power consumption, from implementing the transceiver using a half-rate architecture, to using a highly-shared architecture for the transmit PLLs. Ideally, the FPGAs should have 1–6 quad-channel transceivers, for a total of up to 24 SerDes channels. A number of equalization features allow longer distances and/or the use of low-cost materials in printed circuit boards and backplanes. Special phased-locked loop (PLL) features can deliver user benefits ranging from more flexible clock and baud rate selection, to simplified compliance with radiated-emission requirements, to higher bandwidth options.

Debug and test is also important, including the availability of built-in pseudo-random binary sequence (PRBS) generators and checkers and IEEE 1149.6 “AC JTAG” support for non-DC-coupled signals. Including a built-in eye monitor with debug software support enables designers to debug SerDes without an oscilloscope.  One can optimize the tuning of DFE and CTLE parameters in real time and dial in the ideal settings for the final product (see Figure 2).

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Figure 2: SerDes Eye Monitor Smart Debug Software. (Source: Microsemi)

Solving the Security Challenge

There are numerous threats to the security of a design today.  Everything from the user’s design IP to the manufacturing process can be compromised. 

Critical security techniques and features include hardware roots of trust, strong cryptography coupled with top-notch key management at every stage, and devices with built-in passive and active countermeasures to protect against tampering. Figure 3 shows best practices for secure FPGA provisioning with a unique serial number, keys, and X.509 public key certificate.

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Figure 3: Device Certificate Chain of Trust. (Source: Microsemi)

With these components in place, both design and data security can be addressed. Design security requires that FPGAs utilize the keys and certificate provisioned by its manufacturer, plus other techniques—ranging from patented differential power analysis (DPA) countermeasures to techniques for protecting against side-channel attacks —to protect the user’s IP.  Another way to increase design security is by using physically unclonable function (PUF) technology to generate a hardware intrinsic key.

Data security requires the use of a crypto-processor dedicated to the FPGA user whose core is NIST-certified to implement many of the most commonly used cryptographic algorithms such as AES, SHA 2, ECC, RSA and DH, and includes a cryptographic-grade TRNG. The performance of the user’s crypto-processor should be suitable for many applications, reducing the costs (area, power, and licensing-related) compared with adding an accelerator to the FPGA fabric.

There is growing demand for cost-optimized mid-range FPGAs that deliver significantly lower power at densities up to 500K logic elements (LEs) for communications, defense, and industrial markets.  A new development roadmap has emerged that combines new process technologies and fabric designs with important transceiver changes and security features, enabling FPGAs to address the cost, power, performance and security requirements of mainstream applications while delivering all the benefits of non-volatile technologies.

Ted Marena is the director of FPGA/SOC marketing at Microsemi. He has over 20 years’ experience in FPGAs. Previously Marena has held roles in business development, product & strategic marketing. He was awarded Innovator of the Year in February 2014 when he worked for Lattice Semiconductor. Marena has defined, created and executed unique marketing platform solutions for vertical markets including consumer, wireless small cells, industrial, cameras, displays and automotive applications. Marena holds a Bachelor of Science in electrical engineering Magna Cum Laude from the University of Connecticut and a MBA from Bentley College’s Elkin B. McCallum Graduate School of Business.

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