How GaN and SiC devices can optimize system design of ultra high power density chargers - Embedded.com

How GaN and SiC devices can optimize system design of ultra high power density chargers

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In this article, we will outline how we derive optimal use cases for GaN and SiC power devices in a holistic system optimization approach.

The adoption of wide-bandgap (WBG) power devices such as silicon carbide (SiC) MOSFETs and gallium nitride (GaN) HEMTs is now in full progress across a wide range of market segments. In many cases, WBG power devices are replacing their silicon counterparts and enable higher efficiencies in existing systems. In other cases, such as the totem-pole configuration, WBG power devices enable a simple option for bridgeless power-factor correction (PFC) with continuous-conduction modulation.

In this article, we will outline how we derive optimal use cases for GaN and SiC power devices in a holistic system optimization approach.

Device technology

Infineon Technologies offers the whole spectrum of power semiconductor technologies ranging from its established Si superjunction devices to SiC MOSFETs and GaN e-mode HEMTs. The company’s SiC MOSFETs (see Figure 1a) feature a unique asymmetric trench structure, where the channel mobility is optimized by aligning the channel to the a-plane of the SiC crystal. Furthermore, a large portion of the trench is embedded into a p+ region, which extends below the bottom of the trench and thus reduces the off-state critical field and acts as a body diode. As a result, with Infineon’s trench design compared with planar DMOS concepts, high levels of gate oxide robustness can be reached by allowing lower gate drive voltage for similar RDS(on) performance.


Figure 1: Wide-bandgap semiconductor technologies: (a) CoolSiC (b) CoolGaN GIT HEMT

The basis for analyzing the value proposition of our CoolGaN devices (see Figure 1b) is Infineon’s proprietary gate injection transistor (GIT) technology. This concept has the advantage of separate optimization of on-state resistance and current capability versus threshold voltage, which can increase the threshold voltage without affecting the RDS(on) value. Another advantage is the self-clamping property of the p-GaN gate structure, which acts as a diode and increases the robustness in case of overvoltage spikes on the gate. Another technology-specific advantage is the hybrid drain structure, which injects holes from the drain in hard-switching events and helps to eliminate detrimental effects from residual charges such as dynamic RDS(on) and current collapse.

Wide-output voltage range 240-W USB-C chargers

With the goal of designing the next generation of chargers, an ultra-compact charger supporting two USB-C output ports with 5 A each with an output voltage range of 5–48 V is envisioned. The charger needs to work at universal input AC lines ranging from 90 V to 264 V. Specifically, these wide input and output voltage ranges with two individual ports call for a three-stage approach consisting of a totem-pole PFC stage with two interleaved high-frequency bridge legs, a DCX stage (“DC transformer”) running continuously at its resonance frequency, and two subsequent buck stages. The PFC stage and the DC/DC converter switch at 400 kHz (800-kHz effective frequency with two legs) and 425 kHz, correspondingly. The system employs integrated power stages with CoolGaN GIT HEMTs in half-bridge configuration and matching drivers in all high-voltage sockets and CoolGaN Schottky gate HEMTs as 100-V devices. The entire system achieves an outstanding power density of 42 W/in.3 (uncased). Figure 2 shows the topology and hardware demonstrator.


Figure 2: 240-W charger with two independent USB-C ports and an outstanding power density of 42 W/in.3 (uncased).

Next generations of on-board charger systems with SiC and GaN devices

The current generation of on-board chargers with Si devices achieves about 2 kW/l with phase-modular approaches consisting of three separate PFC stages and three subsequent DC/DC stages. Replacing the high-frequency semiconductor devices with SiC MOSFETs increases the power density to levels of about 4 kW/l. To increase the power density beyond these values, a true three-phase system design has to be considered.

The key enablers for the highest power densities can be seen in the ultra-compact 10-kW EV charging unit shown in Figure 3, which can serve as a blueprint for next-generation on-board chargers. This three-phase EV charging system supports a very wide range of output voltages of 250 V to 1,000 V. It consists of a Vienna rectifier PFC stage and four interleaved dual active bridges (DAB) for the isolated energy transfer to the battery. Both PFC front-end and DC/DC stages are compatible with 600-V power devices due to the three-level nature of the Vienna rectifier and the stacked approach for the DC/DC stages.

For operating the Vienna rectifier at switching frequencies beyond 500 kHz, the switching losses have to be reduced. Hence, we apply a new “synergetic control” strategy, wherein the DC-link voltage follows the six-pulse shape of the rectified three-phase input voltage. This control scheme enables a reduction of switching losses of up to 86%. Instead of switching all bridge legs simultaneously, only the leg carrying the lowest current is switching. Using this technique, an increase of switching frequency to 550 kHz has been achieved. Discrete CoolGaN GIT HEMTs with 70-mΩ RDS(on) are used in the Vienna rectifier front end, while devices with 42-mΩ RDS(on) are employed in the DAB stages.

The DAB stages run between 140 and 400 kHz and achieve zero-voltage switching in most of their operation points.

The entire system achieves a power density of 10 kW/l or 163 W/in.3, respectively, at a peak efficiency of above 95%.


Figure 3: 10-kW EV charging unit supporting a wide output voltage range and a power density of 10 kW/l (163 W/in.3)

The authors would like to thank Professor Johann Kolar, Yunni Li, and Michael Haider from the Power Electronic Systems Laboratory at ETH Zurich for their ongoing cooperation on the EV charging unit.


—Matthias J. Kasper is a principal engineer at Infineon Technologies.

—Jon Azurza is a senior staff engineer at Infineon Technologies.


—Gerald Deboy is a distinguished engineer for Power Discretes and System Engineering at Infineon Technologies.

>> This article was originally published on our sister site, Power Electronics News.


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