You can either spend a month hand-crafting the last few hundred squaremicrons of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumerelectronics industry, achieving short time-to- market is the singlemost effective way of maximizing semiconductor sales and profit. Thechances are you will still be able to push the SoC down the price curveby migrating it to a next generation CMOS process technology within 18months or so.
In addition to providing cost down on existing designs, each newCMOS process is going to allow the design of ever more complex chips.Reducing time-to- market for these new designs will therefore requireyou to manage an ever-increasing level of complexity in a way that cutsboth design and verification times.
It is going to require aggressive changes in the way SoC designs aredriven within the industry, together with partnerships betweencompanies to drive forward standards for IntellectualProperty (IP) interoperability.
The SPIRIT Consortium, a group ofleading companies in the IP supply chain that includes EDA toolvendors, IP providers and integrated device manufacturers, is oneexample of current collaboration in this area.
However, any such standards will only gain widespread acceptance ifthey are effectively deployed within companies and their ability toaccelerate the chip design process is proven.
One of the essential enablers for this is a mechanism that makesproperly configured re-usable IP available to chip designers in a waythat allows them to easily select it, understand it and import it intotheir SoC design environment. The more comprehensive the selection, themore powerful and effective the IP library is.
Using the IP Yellow Pages
One such system being developed by NXP for its internal design teams isa service called 'IP Yellow Pages'. This web-based service, which ishosted on a secure sever, allows NXP's chip designers to browse thecompany's IP libraries and to locate suitable IP with the aid of asearch engine.
For each library entry, an IP Profile web page provides an overviewof the IP's attributes, documentation, deliverables, development statusand level of support. If applicable, it also details any associatedusage, maintenance and royalty fees.
Chip designers can then download the IP they require from the servervia a web-based or command-line interface. The IP Yellow Pages web-siteincludes both hardware and software IP and will soon allow the orderingand order-tracking of use-specific memory configurations.
The site also acts as a shop window for the promotion of new IP thatis added to the IP Yellow Pages library. Much of the IP availablethrough the IP Yellow Pages service is already SPIRIT compliant.
It is equally important to have a system that allows you to assemblethe selected IP speedily into a SoC design. To manage the competingrequirements of increasing complexity and shorter time-to-market, thisdesign environment must be capable of taking SoC design to the nextlevel of abstraction by allowing the rapid generation, configurationand verification of re-usable sub-systems.
It must be able to address system architecture considerations aswell as IP block assembly, steering designers towards sub-system andSoC architectures that are suited both to the application and to theavailable IP.
To cope with the increasing use of IP from third-party IP vendorsand joint-ventures, it should be based on industry standards for IPre-use and commercially supported EDA tools.
These underlying principles are illustrated by NXP Semiconductors'sNx-Builder design environment (Figure1, below ).
|Figure1. Nx-Builder SoC design environment|
SpiRit compliant Nx-Builder is built around a set of SPIRITcompliant EDA tools – Mentor Graphics' Platform Express XML-basedSoC design creation tool framework and Synopsys' synthesis andautomated scripting. Nx-Builder uses NXP Semiconductors'sSPIRIT-compliant IP Yellow Pages as its IP portfolio. These componentscombine to create an environment in which SoC design becomes almost adrag-and-drop exercise. By doing so it is pushing the boundaries ofautomated integration and validation to new levels.
Not only the integration of components is being addressed, but alsothe design flow from an RTL level through all the stepsrequired to get to layout. All the tools in this design flow requireconstraint information in order to be correctly configured.
These constraints are properties of the IP components themselves andthe SoC instance into which the components are being integrated. Theyinclude critical paths and timing constraints, information on clockinsertion, test insertion, layout restrictions and I/O padrequirements.
These constraints can be provided in a generic form and modified asthe integration takes place. SoC production tools can utilize thisinformation so that they are correctly set up, removing another sourceof human error and enabling a high degree of automation in design stepssuch as design for test (DfT ), static timing analysis (STA ), clock and reset insertion.
Support for the insertion of adaptive voltage and frequency islandsand the usage of active power management can also be automated.
The benefits of such a system are considerable. Design andverification cycles are significantly reduced, with functions such asinterconnect verification, infrastructure verification (busses,bridges, memories, register spaces etc.) and IP interoperability beingalmost fully automated.
Chip composition and parameter derivation for reconfigurable IP isimproved, and the system provides a single source for systemdocumentation (flow-scripts, memory maps, interrupt maps, registerspecifications etc.). Such systems not only reduce design risk andencourage future IP re-use. They also enable highly efficient platformreuse.
By providing automated generation of high-quality documentationcoupled with a high-level of design automation they generate chipdesigns that are far less dependent on a single design engineer.
Time-to-market reduction can be as much as 25 percent for new SoCdesigns, and 75percent for straightforward derivatives. Simplifying andautomating SoC design by an order of magnitude compared to previousmethods, environments such as Nx-Builder pave the way for electronicsystem level (ESL) design ” the next paradigm shift in the industry.
|Figure2. ES design facilitates architectural exploration and co-simulation ofboth hardware and software.|
Because these provide behavioral models for hardware IP in alanguage that is essentially the same as the software languages used toprogram SoCs (C or C++), these ESL design environments will allow youto simulate and verify your entire hardware/software design beforehaving to lock anything into silicon.
Hardware/software tradeoffs As a result, they will allow you to makecritical hardware/software trade-offs very early on in the designcycle, thereby minimizing design risk. They will also give you thebenefits of advanced features such as automatic selection ofappropriate system architectures, intelligent debugging and automatedoptimization of RTL output from high-level functional descriptions/models.
In conjunction with compiler development environments that canautomatically generate compilers from SystemC descriptions, they willeven allow you to customize software instruction sets to suit specificarchitectures and application requirements.
These new possibilities will provide an optimum approach thatcombines mature IP reuse with innovative design and new IP creation. Ina business environment where semiconductor companies already have toprovide comprehensive software stacks with their SoCs simply to sellsilicon, the ability to minimize risk and shorten time-to-marketthrough hardware/ software co-design will be an important new enablerfor differentiation.
Ralph von Vignau is directorinfrastructure & standards, chief technology office, NXPSemiconductors.
To read a PDF version of this article, go to “Tme-to-marketdrives SoC design to higher levels of abstraction.”