Signal integrity (SI) has always been a serious issue of concern toanalogue engineers, but with the move towards serial data linksoperating at GHz data rates, the digital hardware designer now equallyhas to pay attention to this vital topic.
High speed serial links between chips are now being adopted for awide variety of applications in order to improve the throughput with anarrower bus width. Some of the latest DSPs and processors, forexample, are being introduced with serial RapidIO.
For many hardware designers, inter-chip communication using busspeeds over 300MHz is a new challenge they have not yet faced.Furthermore, the design of a high-quality data link operating at GHzdata rates requires more care and understanding to ensure thatperformance is not impaired by the effects of board layout and noise.
This article explores SI challenges and considerations that thedesigner must face, and aims to provide a practical guide to overcomingthese challenges. This includes recommendations for the successfulplacing, routing and decoupling of the device on a PCB. A 16-portserial RapidIO switch is described, providing a practical example ofhow these principles may be applied.
The quality of a signal is important at all points within a system, andin serial RapidIO is quantified by the size of the receive eye. The eyeis an infinite persistence trace where the waveform is repeatedlytraced over the previous trace (Figure1, below ).
|Figure1: Typical overshoot and undershoot characteristics on a pulse|
There are many opportunities for the signal quality to becompromised: by the introduction of noise or other random signals ontothe signal path, by poor signal trace routing, by means of eitherconduction or radiation from external sources or by generation withinthe system itself. All of these factors combine to shrink the receiveeye. The areas that need to be considered include:
: Power supply input to the board, outputs of local regulators anddistribution
Clock generation and distribution
PCB substrate material
Board-to-board and backplane connections
Board stack-up and impedance control
Inter-rack connections, cable and connectors
When working at frequencies above 300MHz, the majority of designbest practices that are used for board layout at lower frequencies needto be revised. It is necessary to account for factors that arise as thewavelength becomes comparable to the board dimensions.
This applies not only to the wavelength of the fundamentalfrequency but also to the Fourier components that make up the completewaveform. FR4 material may still be used successfully as a substrate,but the permittivity of the material and the dissipation or loss factorneeds to be considered at higher frequencies.
|Figure2: Scope trace containing an eye diagram|
Through-hole via design also becomes important because unused barrellength, which has a negligible effect at lower frequencies, presents animpedance mismatch in thicker boards and backplanes. The performance ofpost layout simulation is desirable in order to draw attention toroutes of less-than-ideal SI and point out areas of crosstalk.
Particular challenges in terms of on-board SI are created by thepresence of a high-speed processor bus, high-speed memory interface, byclock generation and clock noise, and various sources of board noisesuch as ground bounce, crosstalk etc. Sources of noise can typicallyinclude:
Single-endedparallel buses : switching noise can result from currenttransients necessary to charge/discharge all the lines.
Powerdistribution: inadequate power distribu¬tion aggravates thenoise dilemma, particularly if there is inadequate copper for thecurrent demands, or inadequate or improperly positioned decoupling.
Impedancematching: improper impedance match¬ing results inreflections that can cause overshoot, undershoot and ringing on thesignal lines that make up the differential pair (Figure 2, above) . This results in areduced receive eye and increased jitter in the signal. Thefol¬lowing items are the main causes for mismatch arti¬factsbeing introduced onto a signal, such as (1) changes in routing layers,and, (2) poorly designed escape routing from the device.
Groundbounce: this causes input thresholds to change and can lead tocor¬rupt bits. Serious cases can cause device latch-up, with powercycling required to recover from it.
Crosstalk: this is caused by the close proximity of traces belonging to differentsignal groups. The result of crosstalk in a serial communication linkis closure of the receive eye due to the imposed jitter. Crosstalk iscaused by (1) insufficient track spacing to other signals and (2)poorly implemented serpentines for path length matching. This causesedge advancement as part of the signal takes the short path (jumpinglegs of the serpentine) while the main signal takes the long path.
Clockgeneration: both clock generation and clock buffering can becomenoise generators unless careful attention is paid to details such asEMI filtering components and minimizing crosstalk.
Manufacturers' layout guidelines must be followed in order to obtainthe highest quality clock signals from the device. The consequence of apoorly-implemented clock is jitter in excess of that required by theRapidIO device resulting in poor throughput performance (evidence ofwhich is seen in high bit error rates at the receiver).
How can the designer ensure that these effects are kept under control?First of all, by adequate trace isolation between syn¬chronoussignal groups, and by restricting track lengths and minimizing skewbetween the signals of a differential pair. Routing should be carriedout with a view to limiting parasitics by minimizing the number oflayer transitions.
Vias are costly in unwanted inductance and stray capacitance andshould be kept to a minimum. Usually, two vias per trace is the maximumallowable in addition to the BGA pads.
Choosing the right switch can help to meet the high-speed challenge,while more generally good design practices can help board designerstake control of signal noise resulting from board level traffic. Someof these design features help in limiting external noise sources, whileothers are needed to address noise at the device itself. A properlydesigned package that minimizes parasitics is one of the firstconsiderations, as is the positioning of power and ground pins.
Clock generation circuitry requires particularly careful attention todetail, especially in terms of layout, proper termination and thejudicious use of EMI filtering components. The impedance of the tracesmust also be controlled to avoid unwanted reflections. Improperapplication of these principles can result in clock generators becomingnoise generators. Clock generation and buffering can also lead tounnecessary noise, because of the increased design complexity and theintroduction of routing voids in the power and ground planes.
Pins and packaging
In component package design, it is crucial to use a sufficient numberof power and ground pins as well as placing and partitioning themcorrectly. An inadequate quantity of power and ground pins willincrease the return current path length, which can lead to chip coresupply instability and increased electromagnetic noise. Improper powerand ground pin placement can also negate a decoupling strategy .
The pins need to be properly placed in order to allow decoupling tobe located directly under the package, with minimal trace length tocontrol inductance. Partitioning of core logic power and ground fromI/O power and ground is also critical to controlling noise.
From the perspective of device manufacturing cost, wire bondpackaging may appear to be an attractive option, but from an SI andsystem reliability standpoint, flip-chip mounting offers far moreadvantages. It allows for ample power and ground connections, even fora high signal count package, and power and ground bumps can be used tosurround sensitive I/O bumps.
With wire bonding, the number of pads is limited by the outerperimeter, so a high signal count package leaves very little room forpower/ground connections and necessitates fewer and longer currentreturn paths. The use of solder bumps rather than wires greatly reducesparasitic inductance, since bumps represent much shorter and thickerconnections than wires (Figure 3, below ).
|Figure3. Flip-chip BGA packaging gives much lower parastics than wire bonding|
The length of bond wires also greatly increases the susceptibilityto crosstalk, and imposes slew rate limits on the signal. Using a BGApackage allows the signal and ground connections to be interspersed ina “checkerboard” arrangement, to effectively shield the signal linesfrom interfering with each other.
Cables and connectors
Only cables and connectors specifically designed for high frequency andGbE applications should be used for connecting high bit-rate systems.Use of inappropriate, unshielded or poorly-matched cabling can causeunwanted reflections and pick up interference in a similar way to thatdescribed for on-board discontinuities. Proprietary types of cable forthese applications are availably from a variety of manufacturersincluding Tyco Electronics, Molex and WL Gore.
The impedance requirement of the serial RapidIO interface is 100 ohms.In order to main¬tain this consistent differential impedance, theoptions for the construction of the transmission line are limited toeither strip¬line or microstrip.
Microstrip is used when the signalling must be routed on an outerlayer of the board, while stripline allows the signalling to be placedon an inner layer where shielding by adjacent power and ground planesis possible. Edge-coupled differential (or coplanar) stripline, ratherthan a broadside coupled or dual stripline, is recommended.
Edge-coupled differential stripline is shown in Figure 4 below , along with theequations for single-ended and differential impedance. The stripline issymmetrical when h1= h2. The minimum recommended layer count is six andthe optimum design has 16.
|Figure4. Block diagram of Tsi568A serial RapidIO switch interfaces|
The signal return path is particularly important, and is defined asthe route that current takes to return to its source. This may bethrough ground planes, power planes, other signal paths and throughICs.
The current always takes the path of least resistance. A simple wayto evaluate the integrity of the return path is to draw a loop tracingthe current from the driver through the signal conductor to thereceiver – the smaller the area of the loop, the lower will be theparasitic inductance.
The following design rules apply to all return paths:
Always trace out the return current path and provide as much careto the return path as the path of the signal conductors.
Do not route impedance-controlled signals over splits in thereference planes.
Do not route signals on the reference planes.
Do not make signal layer changes that force the return path to make areference plane change.
Decoupling capacitors do not adequately compensate for a plane split.
Do not route over via anti-pads or socket anti-pads.
If reference plane changes must be made, try to follow the followingrecommendations:
Change from a VSS reference plane to another VSS reference planeand place a via connecting the two planes as close as possible to thesignal via. This also applies when making a reference plane change fromone VCC plane to another VCC plane.
For symmetric stripline, provide return path vias for both VSS andVCC.
Do not switch the reference plane of a signal from VCC to VSS orvice versa.
Guard traces – tracks that run parallel to a signal trace and areconnected to the ref¬erence plane – may be used to minimisecrosstalk, but they take up board space and will be required to be”stitched,” or connected with vias, to the reference plane at intervalsthat prevent resonance.
Due to the high-frequency content of the serial RapidIO signals, itis necessary to minimize the discontinuities imposed by crossing groundand power planes when it is necessary to transition to different signallayers. The use of a controlled impedance via is desirable.
With some forethought, and a knowledge of the basic design rules, it ispossible to apply high-frequency interconnects such as RapidIO to asystem without encountering any of the problems that are traditionallyassociated with poor SI, such as noise, transient effects or crosstalkand jitter.
If traces and signal paths are kept as short as possible, are eithershielded by ground planes or kept physically separated from each other,and if care is taken to avoid mismatched impedances or anyconfiguration likely to support resonance, good SI is easilyachievable. The moral of the story? It is always simpler to avoid SIproblems in the first place – by creating a well thought-out designverified by simulation – than to try and correct SI issues in aproblematic design.
Andre Pirnat is seniorapplications engineer at TundraSemiconductor.