How to simplify power design development and evaluation for FPGA-based systems - Embedded.com

How to simplify power design development and evaluation for FPGA-based systems

Editor's Note: With regard to the System Monitor feature presented in this article, Avalon Microelectronics used this feature in two Virtex-5 FPGAs (XC5VLX330T) in their development with great success. They had an unusual problem on their development board, which shut down when the FPGAs were performing certain functions. Their power management software caused the board to turn off due to certain power threshold violations. Using the Virtex-5 FPGA System Monitor, they were able to dynamically view where these violations were occurring and quickly find a solution. The issue turned out to be a simple miscalculation of a resistor value by their board vendor for one of the voltage regulators providing power to the FPGA. They reduced our debug time by taking advantage of the built-in tools, without the use of expensive debugging equipment.


Power consumption in electronic devices and the design of power systems is an increasingly complex task. Static current levels coupled with increased dynamic current demands imply greater IR drops in power distribution systems. Operating temperature requirements require sophisticated heat sink and airflow measurements. The Virtex-5 FPGA System Monitor features on-die temperature and voltage measurement capabilities that provide valuable information for the development, evaluation, debugging, optimization, and qualification of PCB power designs. This article explains how to configure System Monitor's external channels for power monitoring and provides PCB implementation recommendations/guidelines.

System Monitor Overview
The Virtex-5 FPGA System Monitor has, as its core, a 200 kilo-Samples-Per-Second (kSPS) Analog-to-Digital Converter (ADC). Fig 1 shows a block diagram of the System Monitor.


1. The System Monitor Block.
(Click this image to view a larger, more detailed version)

The System Monitor allows unprecedented and convenient access to vital on-chip analog FPGA information. The inputs to the ADC are on-die temperature and voltage sensors. Using its 17 available external channels, the System Monitor provides for the measurement of the physical environment of the PCB or enclosure. The control logic implements common monitoring features, including automatic channel sequencing, filtering, and alarms. All of these features are user programmable and can be customized at run time through the register file interface accessible in the FPGA logic through the Dynamic Reconfiguration Port (DRP). The DRP is a standard bus interface available in many Xilinx FPGA blocks. This port enables updating the configuration of a particular block in a dynamic manner. Alternatively, the register file interface is accessed externally through the JTAG Test Access Port (TAP). Indeed, access to the System Monitor feature is available even before the device is configured using the JTAG TAP.

Power supply validation
Increased current demands along with reduced power supply voltage complicate power system design by heightening the sensitivity to resistance in the power system. Reduced supply voltages imply reduced margin for inaccuracies in the power supply voltage. That is, the absolute value of the tolerable error scales with the power supply voltage itself. For example, the tolerance on the 1V VCCINT supply level is specified at ±5% or ±50mV. With a 5A current demand, an unaccounted series resistance of just 10 micro-ohms in the PCB power system, and a power supply nominally set to 1V, the DC level of the delivered power supply is already at its specified lower limit (i.e., 0.95V due to the 50 mV PCB voltage drop between the regulator and the Virtex-5 device when 5A goes through the 10 micro-ohms PCB resistance).

Modern BGA type packages make it virtually impossible to attach a physical probe to the ball of the device; consequently, the actual level of the power supply received by the FPGA is difficult to determine. The System Monitor resolves this issue. For the first time, an accurate measurement of the actual on-chip power supply is made available and is simple to employ. The internal power supply sensors incorporated in the System Monitor function allow, to an accuracy of 1%, the on-die measurement of the VCCINT and VCCAUX power supplies.

Accurate knowledge of the power supply level, measured right at the device die, gives the development engineer a key piece of information required in determining the desired DC set point of the power supply. This knowledge eliminates the need to build in excess margin due to a lack of understanding of the voltage drops between power supply source and load. Excessive margin in the power supply level is expensive in terms of power consumption. Static power dissipation is approximately proportional to the cube of the DC voltage level. Dynamic power dissipation is proportional to the square of the DC voltage level. For example, a 2% reduction in DC supply level implies approximately a 6% reduction in static power consumption and approximately a 4% reduction in dynamic power consumption.

The System Monitor's external channels can be used to measure other power supplies at some point on the PCB. The only restriction is that the levels applied to the System Monitor inputs, for measurement, must fall within System Monitor's specified input range. Implementation of a simple resistor ladder to attenuate a supply with a level in excess of 1V is illustrated in Fig 2 .


2. Power supply measurement.
(Click this image to view a larger, more detailed version)

In Fig 2 , the signal is attenuated 5x before measurement by the System Monitor, which measures the 0.5V level in unipolar mode and returns a code representing this level. This measurement result is then scaled 5x to translate back to the intended power supply level.

There are some important points to note with regard to PCB implementation as follows:

  • To ensure accurate attenuation, the resistors used to create the ladder attenuator must be precise. 
     
  • The routing of the inputs to the System Monitor must be accomplished in a tightly coupled differential manner. Keeping these traces tightly coupled ensures that any potential noise pickup is common mode and will be differentially rejected by the System Monitor. 
     
  • In addition to any implicit bandwidth limiting circuitry in the input paths to the System Monitor, a low pass (anti-alias) filter network must be placed on the external analog input pairs, as close a possible to the device pins. This filter is designed to attenuate high frequency components entering the ADC and limit corrupting the measurement.

As with all System Monitor outputs, this data is available over the JTAG TAP. The standard JTAG infrastructure of the PCB can be used to assess the integrity of the prototype power system, even in advance of the FPGA bitstream being finalized. Of course, when assessing IR drops, measurements need to be made when the current demand is present.

Real-time VCCINT power measurement
During the development/evaluation phase of a system design, a System Monitor application, in conjunction with an external shunt resistor, is useful for power measurement on the VCCINT power supply. This measurement is easily set up as illustrated in Fig 3 .


3. VCCINT power measurement.
(Click this image to view a larger, more detailed version)

The System Monitor can be used to measure the voltage (VKELVIN ) dropped across the low ohmic precision shunt resistor. With a known RSHUNT and with VKELVIN across the shunt being accurately measured by the System Monitor, the value of ICCINT can be determined. For values of VP less than or equal to 1.1V the measurement should be made in the System Monitor's bipolar mode.

Example Calculation:

RSHUNT = 10 mΩ
VKELVIN = 100 mV (as measured by the System Monitor)
VCCINT = 1V (as measured by the System Monitor)

In this case, the System Monitor measures a 100 mV drop across the shunt resistor.

VKELVIN = ICCINT × RSHUNT
=> ICCINT = VKELVIN / RSHUNT
=> ICCINT = 100 mV / 10 mΩ
=> ICCINT = 10A

PCCINT = VCCINT × ICCINT
=> PCCINT = 1V × 10A
=> PCCINT = 10W

The System Monitor uses a 10-bit ADC to measure the VKELVIN to a resolution or relative accuracy of 1 bit (~0.1% of full scale or 1 mV). In the previous example, this 1 mV is therefore 1% (1 mv / 100 mV) in the current and power measurement.

Other external methods of preconditioning the VKELVIN signal through an instrumentation amplifier with precision resistors are not documented here, but can be used to reduce the 1 mV to much less than 1% of the measurement range.

When implementing this sensor on a PCB, it is important that the voltage dropped across the shunt resistor is compensated for by the power supply. This ensures that the FPGA receives the correct voltage level at its VCCINT inputs. This can be achieved by using the power supply's sense inputs to measure the VCCINT value at the point of load. System Monitor's on-die measurement of the DC level of VCCINT can be used to inform the set point of the power supply.

Just as for all external measurement implementations, it is necessary to ensure that the routing of the inputs to System Monitor are done in a tightly coupled differential manner and have an anti-aliasing filter to reduce the effect of common-mode noise sources.Static power consumption estimation with accurate junction temperature data
External solutions for junction temperature measurement are possible; for example, thermal diode monitors can provide accurate die temperature measurements. However, in addition to the requirement for the external monitoring device itself, the solution can be difficult to apply and is sensitive to noise and other implementation details. The System Monitor's integrated temperature sensor eliminates these complications.

The System Monitor's integrated temperature sensor provides the user with an accurate, center of die, junction temperature measurement. The convenient access to this data via the fabric or the JTAG TAP implies completely that unobtrusive measurement and disturbance of the airflow or other environmental conditions is avoided.

Knowledge of the device junction temperature offers significant advantages at the development/evaluation phase. In a debug situation, monitoring temperature changes and correlating the timing of exceptional temperature fluctuations with events taking place in the design or system provides an exceptional design tool. Temperature can be monitored during periods of heavy current demand, leading to a faster diagnosis of potential issues.

Since designs must meet a power budget, the knowledge of the actual device junction temperature is vital to determine the power dissipation of the design (see also the Xilinx whitepaper wp246.pdf).

Often, the exponential relationship that exists between static power dissipation and temperature is not properly considered when making power estimates. Unrealistic estimates of static power dissipation are often assumed because of actual device junction temperature is unknown. Many customers using the System Monitor are surprised at the junction temperatures reached in their designs. Some designs show a 50/50 relationship between static and dynamic power dissipation, thus intensifying the need for accurate estimation of static power consumption. As shown in Fig 4 , extrapolation/projection of the junction temperature from ambient or external probing is likely to be grossly inaccurate. Using the System Monitor removes this uncertainly.


4. Normalized leakage current versus device junction temperature.
(Click this image to view a larger, more detailed version)

“Set and Forget” environmental monitoring
A background monitoring system for environmental conditions is another useful capability in a system debug or runtime scenario. The System Monitor integrates a user customizable alarm system on its internal sensor channels. The system caters to automatic alarm signal generation on over-temperature or over/under voltage conditions. The thresholds settings for the alarms are user defined. The alarm signals are made available in the FPGA logic. A simple use model of this facility is accomplished by wiring the alarm output signals to onboard error LEDs. A more involved use model uses the alarm functionality in processor controlled system management solutions.

Graphical display of environmental conditions
Users familiar with the ChipScope Pro debugging tool know that it inserts logic analyzer, bus analyzer, or virtual I/O low profile software cores directly into a design to view internal signals or nodes. The ChipScope Pro tool also supports access to the Virtex-5 FPGA System Monitor function. Within the ChipScope Pro tool, a user, in addition to capturing logic status of a design, can capture a picture of the physical environment on chip and potentially beyond, depending on utilization of the System Monitor external channels. After the ChipScope Pro tool is invoked, it automatically detects the presence of the System Monitor on the JTAG chain and makes a console available to the user for access to the feature (see Fig 5 ).


5. Accessing the System Monitor using ChipScope Pro over JTAG.
(Click this image to view a larger, more detailed version)

In the default mode, the ChipScope Pro tool's System Monitor console (Fig 6 ) plots the temperature, VCCAUX and VCCINT data measured through the internal sensors. In addition to this data, the console allows the user to display any one of the System Monitor's external channels, at any given moment. The ChipScope Pro tool also provides a time stamped data logging facility for further analysis of these measurements. The temperature and voltage data provided by the System Monitor is extremely useful in development, debug, and evaluation scenarios. Access to this resource requires little or no design effort.


6. The ChipScope Pro tool's System Monitor console.
(Click this image to view a larger, more detailed version)

In addition to plotting and data logging facilities, the ChipScope Pro tool also provides full read/write access to the System Monitor's register file interface through the JTAG TAP. This access is available from power up. No FPGA configuration is required to access the System Monitor through the ChipScope Pro tool. The ChipScope Pro tool interface allows a user to customize the complete suite of System Monitor functionality.

Conclusion
The Virtex-5 FPGA's unique System Monitor feature provides easily accessible and valuable analog data requiring minimal design effort. This data, which can be leveraged during the development/prototyping/evaluation phase, represents a real value proposition to the development engineer since it offers a unique insight into the power system. IR drops in the power distribution system can be monitored and potential issues with the power supply or PCB implementation can be quickly identified.

The JTAG TAP, along with the ChipScope Pro tool allows full access to the System Monitor feature in a quick, convenient, and efficient manner. The System Monitor's temperature sensing capabilities deliver an accurate measurement of actual device junction temperature for use in determining a realistic estimate of power consumption. The System Monitor feature, in conjunction with an external shunt resistor, enables the measurement of power consumption on the VCCINT supply.

To enable the System Monitor, the required PCB connections and components must be in place. For further details on the Virtex-5 System Monitor feature and its associated power supply, reference, and PCB implementation guidelines, see the Xilinx System Monitor web page. Also, the System Monitor User Guide is available on the web.

Pádraig Kelly has ten years' experience in the semiconductor industry. He currently works as a senior mixed signal IC design engineer in the team responsible for the development of the System Monitor feature at Xilinx.

Pádraig began his career as a hardware design engineer at Tellabs. He holds a B.E. in Electrical/Electronic Engineering from University College Cork, Ireland.

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