The need of systems companies for higher throughput while reducing thetime and cost of developing advanced PCB systems has pushed ICcompanies to design advanced Serdes I/O architectures.
These architectures contain feed forward equalizers, decisionfeedback equalizers, and clock and data recovery circuits which aredifficult, if not impossible, to model using current modelingstandards.
Moreover, with these new architectures, the point to view thequality of signal (open eye vs. closed-eye) moved from package pin toinside the IC, after the clock and data circuit is recovered from thesignal. This has created a problem for measurement equipment vendors aswell.
On the PCB, theSerdesdevices drive differential pairs called serial links. The need forhigher bandwidth and faster throughput has resulted in very highreliability requirements for serial links at the system level. Somestandards require that the bit error rate (BER) for such serial linksbe no more thanone error in 1012 bits transmitted on the serial link.
To ensure that the serial link is designed at the board level,systems companies must either simulate serial links with models ofSerdes transceivers or build a fully functional physical prototype ofthe system. Simulation is preferred over building physical prototypesto reduce costs and to shorten design cycle time.
|Figure1: Higher frequencies ushered for a new approach in modeling advancedSerdes I/O architectures.|
To perform these simulations, systems companies require models from ICcompanies that can be used in commercial PCB simulation environments.Simulation environments should be able to predict the behavior ofserial links with a very long stream of data (over 10 million bits) ina reasonable amount of time.
Since current I/O modeling standards are heavily dependent ondevice/circuit level modeling techniques, IC companies, over the lastfour years, have developed their own internal Serdes I/ O modeling andserial link simulation environment to validate and correlate theirdevices.
Due to lack of tools that could consume these models, IC companieshave been forced to distribute their internally developed tools tosystems company customers to evaluate their Serdes intellectualproperty.
IC companies would prefer systems companies to use their IP on bothends of the serial link. However, it is highly probable, that on theother end of a serial link, IP from a different IC company is deployedresulting in an interoperability problem for systems companies. At thesame time, IC companies do not want to be in the EDA business -developing, distributing and supporting PCB simulation tools.
IC companies would prefer to have an industry standard modelingapproach that allows them to model the behavior of their advancedSerdes IP while protecting their IP when models are distributed tosystems company customers.
A new approach is then required to address the modeling needs ofadvanced Serdes IP companies. The key requirements on any new approachthat have been echoed by Serdes IP companies include:
1) Ability to model complexDSP-like behavior (filter optimization, decision feedback equalization,clock and data recovery);
2) High accuracy (hardwarecorrelated) with minimum simulation time;
3) Protection of Serdes IP;
4) Ability to model andevaluate IP before silicon is developed (pre-silicon) and;
5) Availability as a publicstandard that is supported by EDA vendors (which would solve theinteroperability problem)
Enhancing IBIS with BIRD104
A proposal has been submitted to enhance the I/O Buffer InformationSpecification (IBIS) BIRD104 (Buffer Issue Resolution Document) whichwould then allow IP vendors to create executable algorithmic modelsthat plug into the PCB simulation environment. The proposal is uniquein many ways.
First, it gets support from key EDA companies and Serdes IP vendors.Second, before introducing the proposal, EDA and IP vendors havedeveloped software and model to prove that the concept works. Third,Algorithmic Modeling Interface toolkits have been introduced anddistributed (through the IBIS Website) for thoseinterested in developing and testing the algorithmic model approach.
So far, IBIS worked with a fixed I/O model ('B' driver) that wasintegrated into EDA vendors' PCB simulators, while IC companiesprovided parameters to describe their I/O drivers and receivers.
In other words, there was only one model that was used to describethe behavior of I/O buffers. This approach worked well until around2003-2005. With advanced Serdes I/O architectures, there is a need tomove the model behavior definition from inside the EDA vendor tools toinside the I/O buffer model using a “black-box” model approach, and todefine the interaction between the “black-box” model and the EDAplatform.
|Figure2: Over 20 percent of the models given by IC companies to systemsvendors are HSpice.|
With this proposal, IBIS enters a new era – with executablemodels – where behavior is simulated inside the I/O model instead ofinside the EDA platform. This provides IP vendors greater flexibility,enabling them to model new architectures without waiting for IBIS tochange.
BIRD 104 is a first step toward this direction. Over time, it willbe enhanced to handle more architectures and additional behaviors. Withthe black-box approach, it is capable of handling more Serdesarchitectures than the previous approach.
Originally developed by Cadence and IBM, the proposal which allows IPvendors to model advanced Serdes devices is language agnostic. Itenables IP vendors to create a black box model that interacts with theEDA platform through a simple, yet powerful, C-based API.
Since the black box model is to be delivered to systems companies asshared object or a dynamically linked library, this new approachobfuscates the contents sufficiently to help Serdes vendors protecttheir IP.
With the ability to model advanced Serdes devices at algorithmiclevel, the models can be extremely fast – allowing EDA platforms tomeet the need of systems company users to simulate huge data streams ina very reasonable amount of time. Interoperability of models can beachieved when BIRD 104 is adopted and supported by EDA companies andSerdes IP developers.
The ability to model advanced Serdes behavior using algorithmsallows IP vendors and systems companies to do pre-silicon explorationand IP validation, as well as the targeted serial links in PCB designenvironment.
To perform BER tests and to output bathtub curves, measurement toolshave to emulate a receiver (or at least the CDR circuit). Themeasurement tools have to assume an RX model to perform these tests.With algorithmic models, the tools have a real model of a receiver,thus removing any assumption from the equation.
Algorithmic models, hence, make it possible to bring the samesoftware to the measurement and EDA platforms. This unprecedentedtie-up between the two platforms results in better correlation betweensimulation and measurement.
Cadence has developed and distributed Algorithmic Model DevelopmentKits to help IP vendors learn this new approach, and to develop anddistribute algorithmic models that can work with PCB simulationenvironment.
Recently, an updated version of the toolkit was released through theIBIS Website for doing “proof of concept” tests for interoperability ofalgorithmic models. Users can download toolkits that contain samplemodel code, a basic tester executable that can test the model and basicdocumentation.
Algorithmic modeling methodology gives designers flexibility inmodeling their device accurately while providing them with all the IPprotection they need.
It brings a revolutionary change in which complex multi-gigabittransceivers can be modeled for high-speed I/O circuits. Backed bymultiple EDA vendors and IP companies, this technology will givesystems companies interoperability and the ability to simulate huge bitstream to predict BER without the need to build physical prototypes.
Hemant Shah is Product Marketing Director at Cadence Design Systems Inc.