HP and STMicroelectronics Launch "Lx" - Embedded.com

HP and STMicroelectronics Launch “Lx”



To read original PDF of the print article, click here.

HP and STMicroelectronics Launch “Lx”

Alexander Wolfe

A new VLIW architecture promises to shake up the system-on-chip design world.

As buzz builds around the new approach toward embedded chip architectures called system-on-chip, two companies have teamed together to come up with what they think is a better mousetrap. This new family of embedded processors, which is designed to be more flexible and provide better performance at lower power dissipation and lower cost than traditional SOC approaches, will make its debut this month at the Microprocessor Forum in San Jose, CA.The ground-breaking architecture, known as “Lx”, evolved from a collaboration between Hewlett-Packard Labs, in Cambridge, MA, and France-based STMicroelectronics.

“The fundamental thing we believe is that, at any level of technology, we can produce a VLIW processor that's two to 10 times faster than an equivalent RISC processor,” said Roger Shepherd, manager of advanced architectures at STMicroelectronics' Bristol, England labs. Shepherd also serves as ST's lead representative on the project, which is centered at HP's labs in Cambridge, MA.System-on-chip, in general, refers to hardware runs where time-to-market and cost are critical factors. The chips themselves are often ASIC-based solutions, consisting of a central microprocessor core or a DSP core and multiple peripheral functions. However, reining in the engineering costs for small-volume designs-even when off-the-shelf cores are used-has remained an industrywide challenge.

New twist
Enter Lx. In fact, the Lx team has not eschewed SOC; they've just gone about it in a slightly different manner, one they believe gives the concept a little more utility.

The Lx architecture consists of a family of cores, according to Josh Fisher, head of HP Labs. Fisher is often referred to as “the father of VLIW” for his cutting-edge work on the technology at Multiflow Computer in the 1980s.

“It's a core for a SOC, but it's a family which has been designed for your domain of application, and typically designed with a large customer in mind,” said Fisher. High performance comes from its VLIW heritage, which gives it the ability to exploit instruction-level parallelism (ILP). It is also customizable for different application domains.

“Lx is also enhanced by the fact that the customized cores all 'feel' to the user like they're in the same family,” said Fisher-something that's previously been difficult to achieve with VLIW designs. “So, we were able to do customization without a lot of incremental engineering and cost to the customer.”

Lx's creators reiterate that it is intended to be used in system-on-chip configurations, where it can be married up with appropriate additional processor capabilities and desired peripherals. It's certainly not being touted as a general-purpose microprocessor, which requires a notoriously expensive infrastructure of development tools. One possible application would be in a set-top box, where the multiple Lx cores could be configured on a single chip to handle, for example, general-purpose processing, MPEG decoding, and streaming media data types.Although HP and ST do not like to use DSP in regards to Lx-“DSP is too specialized”-they note, perhaps the Lx is more DSP-like than anything else. (Strictly speaking, the companies see Lx as a convergence of DSP and microcontroller.)

Indeed, the Lx prototypes, which are due by the end of the year, will enter a DSP market that's been flooded by new devices and turned into a testbed for everything from reconfigurable computing DSPs to VLIW design. Competitors will likely run the gamut from high-flying upstarts such as the reconfigurable chips from Tensilica, through to VLIW DSPs such as Motorola's StarCore, TI's TMS320C62xx family, and Phillips' Trimedia. Also sure to remain in the mix are tried-and-true general-purpose platforms such as MIPS and ARM.

Under the hood
For each potential customer, the Lx custom processors would be architected by an automated hardware/software co-design process. Such chips would be churned out in very low volumes for specific, deeply embedded applications.

A major impetus for the venture is a perceived need to supply the burgeoning demands of smart embedded devices such as Web processors, car navigation systems, and other new-age consumer-electronics devices being suggested by Internet designers.

The approach rests on two bedrock concepts, according to the two companies. First, there is Lx's new clustered VLIW core architecture (see Figure 1) and microarchitecture specialized to an application domain that ensures scaleability and customizability.Next, HP and ST have developed a toolchain they say is based on “aggressive ILP technology.” This is intended to give the user a uniform view of the platform at the programming language level.The first major peek at the Lx project came in June, when engineers from the two companies delivered a joint paper on the effort at the 27th Annual International Symposium on Computer Architectures in Vancouver, B.C.

Figure 1

In terms of design, the basic Lx is laid out as a cluster of four VLIW execution units. That is, the low-end design would be a four-issue machine containing four 32-bit integer ALUs, two 16-by-32 multipliers, one load/store unit and one branch unit.

One level up in the family, an eight-issue device could be constructed by ganging together two clusters. The added cluster would bring along its own set of registers, along with other detritus to minimize the difficulties inherent in scaling up a processor.

Lx also relies on a two-level code compression scheme. The instruction cache is compressed so that unused slots don't consume space during encoding, the companies' engineers write. More ambitious is an effort in the works to compress binaries with Huffman-like techniques and then decompress blocks of instructions during I-cache refills.

To clarify each company's role in the overall effort, so far as is known publicly, HP developed the instruction set architecture and much of the software behind Lx, while ST implemented the hardware.”The Lx project has concentrated on producing a highly automated way of exploring architectures,” said Shepherd. “Not on implementing them, but exploring them.”

Though Shepherd's statement sounds cryptic, he really means that the process is not yet entirely hands off. Right now, the tools output a compiled description of the device that must be tweaked. However, he sees things moving in the direction of eventual full automation.In a separate effort that delves into some of the same concepts as Lx, HP is also working on a project called the PICO Architecture Synthesis System. (PICO itself stands for “Program In, Chip Out”). Led by Bob Rau, out of HP's labs in Cupertino, CA, PICO also aims to create a set of software tools that could make it economically feasible to quickly roll custom processors in low volumes for specialized embedded applications.

However, PICO appears to be working with more complex cores, akin to HP and Intel's highly advanced IA-64 architecture. Lx takes a more downsized tack, both in terms of power consumption and complexity.

Alexander Wolfe is editor-at-large for ESP. He holds a BE in electrical engineering from Cooper Union. He has written assembly language code for embedded systems. He is co-author of From Chips to Systems: An Introduction to Microcomputers, 2nd Edition (Sybex, 1987). He can be reached at .

Resources
Faraboschi P., G. Brown, et al. “Lx: A Technology Platform for Customizable VLIW Embedded Processing,” is available at www.hpl.hp.com/cambridge/projects/cfp/docs/ISCA00_paper.pdf.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.