IAR Systems and Andes collaborate to boost performance for RISC-V users

IAR Systems and Andes have formed a partnership in order to deliver powerful development tools for Andes’ RISC-V-based solutions. IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench. The toolchain offers leading code performance for size and speed, as well as extensive debug functionality with a fully integrated debugger with simulator and hardware debugging support. Since 1983, IAR Systems’ solutions have ensured quality, reliability and efficiency in the development of over one million embedded applications. The strong technology offering is accompanied by IAR Systems’ renowned technical support and services.

Andes Technology develops high-performance, low-power processors and their associated SoC platforms, and they have created a rich series of 32-bit embedded CPU core families with a record of more than 2.5 billion accumulated units of Andes-Embedded SoC shipped globally by end of 2017. Andes provides the RISC-V cores, AndesCore N25(F)/NX25(F) and A25/AX25, with AndeStar V5 instruction extension and leading Andes Custom Extension instruction customization capabilities. The AndesCore families are being used for a wide range of smart emerging applications including satellite navigation, high-precision sensor fusion, advanced smart meters, smart wireless communication, networking, voice processing, ADAS, storage, and machine/deep learning. To further boost the performance in the target applications, and to ensure code density, Andes and IAR Systems collaborate to support the cores in IAR Embedded Workbench.

Support for Andes cores will be provided in IAR Embedded Workbench for RISC-V. The toolchain is currently under development and the first version will be available in mid-2019.

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