Claiming it is an industry first, Integrated Device Technology has taken the wraps of a family of low jitter timing circuits .for Smart Grid and industrial automation and networking designed to improve the accuracy and reliability of applications using the IEEE 1588 time transport and stamping protocol.
Also incorporating an integrated Ethernet digital PLL (DPLL) and digitally-controlled oscillator (DCO) in a single chip, IDT's 8V89316 and 8V89317 low-jitter Ethernet PLLs used to frequency synchronize switches and routers via the Ethernet physical layer to improve the reliability and time accuracy of IEEE 1588-based transparent clocks, boundary clocks, and ordinary clocks.
Louise Gaulin, vice president and general manager of the Network Communications Division at IDT, said the 8V89316 generates clocks suitable for QSGMII (Quad Serial Gigabit Media Independent Interface) and 1 GbE interfaces, while the ultra-low-jitter 8V89317 is suitable for 10 GbE interfaces and adds the ability to lock to 1 PPS (pulse per second) GPS clocks. Both devices include DCOs for increased flexibility, allowing them to lock to an incoming Ethernet clock or synthesize their own IEEE 1588-based clocks that other devices in the system can use as a frequency reference.
“The 8V89317 can lock to a 1PPS frequency reference from a GPS receiver, allowing use as part of a local network master clock without the need for wire- or fiber-based access to a synchronization source,” she said. “GPS timing improves flexibility of the physical location of a clock and reduces installation costs for ‘timing islands’ by eliminating the need to extend a timing network to every location.”
The 8V89316 achieves phase jitter below 650 femtoseconds RMS over the 10 kHz to 20 MHz integration range, making it appropriate for 1G Ethernet PHYs and QSGMII (Quad Serial Gigabit Media Independent Interface). The 8V89317 phase jitter is below 300 femtoseconds RMS over the 10 kHz to 20 MHz integration range, capable of meeting the most stringent 10G or 40G Ethernet PHY jitter performance requirements.