SAN FRANCISCO — There’s still a lot of life in Moore’s Law and a lot of smart people driving it forward and putting it to good use. That was my big takeaway from the 2014 International Electron Devices Meeting.
IEDM was a victory lap for Intel, which gave more details on the 14 nm finFET process it first described in September. IBM chomped at its heels, describing its own 14 nm finFET process optimized for its embedded DRAM.
Separately, TSMC gave a first, albeit somewhat limited, look at its improved 16 nm+ finFET process. Two of its customers — Avago and Renesas — gave the first public descriptions of prototype devices made in it.
Samsung presented eight papers but none that described its 14 nm process. That’s a good sign it is probably coming soon, but development was still too immature when papers were due in late June.
The event put to rest any doubt finFETs are the way forward for the bulk of the industry. STMicroelectronics was the lone voice advocating a planar silicon-on-insulator alternative.
Other than Samsung, no one else delivered papers on 3D NAND flash. All its competitors are probably working on it but are too close — or far away — to reveal their exact status.
Likewise, IEDM veterans thought they would have seen more papers on topics such as tunnel FETs and III-V materials that could be key for the 10 nm node and beyond. The lack of papers suggests rivals such as Intel, IBM, Samsung, and TSMC may be in the late stages of finding their secret recipes.
An estimated 1,575 engineers attended the event that included 218 papers ranging from a MEMS-based tweezers that could squeeze a strand of DNA to an ultra-dense array of carbon nanotubes.
The event opened with a short course on the challenges of design at 7 nm. The extensive set of talks detailed so many options in areas such as high-mobility channel materials that one researcher said it “shows no one knows what to do.”
For me, the good news is there are many options and lots of smart people checking them out. Enrico Prati, who works at a national nanotech research center in Italy, is just one of those engineers.
“It’s time to fully exploit the power of self-assembly to bridge the gap from today’s lithography to sub-nanometer devices,” he told the audience in a plenary talk. “We can reverse our approach and explore” the factors impeding such designs as just possibly the forces that can enable them, he said.
In a separate panel discussion Applied Materials hosted in parallel to IEDM, Intel senior fellow Mark Bohr, now working on 7 nm technology, expressed his optimism for the road ahead.
In development and research, we see scaling continues at least another 10 years, which is the same answer we gave 10 and 30 years ago. It’s hard to see beyond 10 years.
Although it gets harder every time, we are still developing technology that’s lower cost-per-transistor than the previous node. I remember when one micron was terrifying to us.
Today our 22 nm process is Intel’s highest yielding, lowest defect technology. In a year or so, our 14 nm process will match that, but it will take a lot of work.
The heady challenges of design at 14 nm made the node later than expected for Intel, closer to a three-year than to Intel’s typical two-year cadence. “We don’t expect we’ll have similar problems at 10 nm, because we’ve learned and we’re trying harder,” he said.
To read more of this external content and other news at IEDM, go to “Intel runs a 14 nm victory lap.“