The IEEE has just formed two new standards working groups for system level power modeling and SoC hardware abstraction: P2415 Unified Hardware Ab straction and the P2416 Power Modeling Meta-standard .
According to Stan Krolikoski, chair of the IEEE Computer Society’s Design Automation Standards Committee (DASC), which is sponsoring both working groups, the efforts are are intended to support development of more powerful and economically affordable electronics.
“Mobile and wall-powered consumer devices continue to put stringent demand on battery performance, energy consumption and heat dissipation, which requires systems to implement many complex power-aware operational modes,” said Krolikoski, “therefore, it is very important that the low-power design methodology for system-on-chip in use today continues to extend into the system and software domain covering complete electronic devices.
He said the proposed IEEE P2415 “Standard Project for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems” is intended to define the syntax and semantics for energy-oriented description of hardware, software and power management for complete electronic systems.
“It will enable specifying, modeling, verifying, designing, managing, testing and measuring the energy features of an electronic device, covering both the pre- and post-silicon design flow,” said Krolikoski. On the hardware side, the description will address enumeration of on- and off-chip components, memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, energy and power attributes.
“On the software side, the description will address software activities and events, scenarios, external influences and operational constraints, and, on the power-management side, the description will address activity-dependent energy control,” he said.
The new standard, once completed and approved, will be intended to be compatible with the current IEEE 1801-2013 (UPF) standard to support an integrated design flow. Additionally, the new standard would complement functional models in standard hardware description languages IEEE 1076 (VHDL)2, IEEE 1364 (Verilog), IEEE 1800 (SystemVerilog), and IEEE 1666 (SystemC), by providing an abstraction of the design hierarchy and an abstraction of the design behavior with regard to power and energy usage.
“IEEE P2415 will provide the higher level of energy abstraction for the system-on-chip and the whole device and, therefore, will enable earlier (more abstract) modeling of power states using the IEEE 1801-2013 (UPF) standard,” said Dr. Vojin Zivojnovic, chair of the IEEE P2415 working group and CEO of Aggios, Inc.
“Many software engineers and system architects will find this effort well-aligned with their need to communicate their low-power and energy requirements with the hardware engineers in an aligned fashion for holistic, quantifiable and reusable energy optimizations.
Krolikoski said the P2416 effort is being created to propose a meta-standard focused on parameterization and abstraction, enabling system, software and hardware IP-centric power analysis and optimization. This standard, once completed and approved, will define the required concepts and semantics for the development of parameterized, accurate, efficient and complete power models for systems and hardware IP blocks usable for system power analysis and optimization.
These concepts include process, voltage and temperature (PVT) independence, power and thermal management interface, workload and architecture parameterization. Resulting models will be suitable for use in both software-development and hardware-design flows, as well as in representing both pre-silicon estimated and post-silicon measured data.
“This standard will define the necessary requirements for the information content of parameterized, accurate, efficient and complete power models, to help guide development and usage of other related power, workload and functional modeling standards,” said Dr. Nagu Dhanwada, chair of the IEEE P2416 working group and technical lead for Power Tools and Methodology in IBM Systems and Technology Group.
“Beyond defining the concepts and related standard requirements, the proposed specification will recommend the use of other relevant design-flow standards with the objective of enabling more complete and usable power-aware design flows. I invite experts from diverse power-modeling domains to contribute to this open and transparent process.”