One of the toughest obstacles faced bydesigners of embedded real-time systems comes from the same newtechnology that fuels this fast-moving industry. Our insatiabledemand for more powerful, smaller, and less expensive processorsand peripherals has driven the wizards of silicon to producegeneration after generation of increasingly fasterdevices.
However, system infrastructures for connecting these devices toeach other and to real world peripherals have not kept pace withthe data transfer demands of the new devices. In trying to closethis I/O gap, Pentek has developed the VIM (Velocity InterfaceMezzanine) architecture, a new royalty-free, open-system,high-performance mezzanine bus delivering extremely high-speed datatransfers suitable for a variety of processors and boardformats.
Real-time system performance often suffers more from bottlenecksin interconnections than from device speeds. For details on datarates for new processors, see New ProcessorsDrive the Data Rates.
Several techniques have evolved to address this problem inopen-architecture, board level embedded systems, but each has itsdrawbacks. The role of the backplane in these systems, for example,is shifting from its traditional task of providing a data flowchannel between boards to that of handling control, status andinitialization tasks.
Even though some newer high-speed backplane technologies areemerging, the concept of arbitrating for a common bus shared acrossmultiple boards proves limiting in the more demanding applications.As a result, alternative techniques for moving data across thebackplane, like RACEway, have grown in acceptance, although thecost of implementation and packaging can be significant.
One of the most traditional methods of delivering dedicated,high-speed interconnects between boards is the mezzanine ordaughter board. Over the years, dozens of mezzanine architectureshave evolved.
Most were inspired by the specific needs of a particular productor manufacturer and, therefore, remained obscure, companyproprietary designs. However, after years of use, refinement,definition and numerous committee meetings, a few mezzanine designshave evolved into true industry standards. Unfortunately, the mostpopular standard mezzanine busses still fall far short of meetingthe needs of recently introduced DSP and RISC processors. Fordetails on differing mezzanine design standards, see Comparing Mezzanine Designs.
Pentek ran up against this shortfall when trying to meet thehigh-speed I/O demands of the Texas Instruments TSM320C6201 on ourquad processor VMEbus board, the Model 4290. Pentek needed amezzanine structure that could provide a private parallel data pathto each processor supporting up to 100MHz transfer rates for 32-bitwords.
We also wanted to accommodate high speed serial interconnects tospeeds of 100Mbits/sec, especially well suited for the many digitaltelecom interfaces and other serial peripherals. Front panel accessfor the many different types of signal interfaces and the widevariety of associated connectors was also essential. In addition,provisions for shielding of critical analog and RF circuitry wererequired for supporting wideband data converters and software radiofunctions.
Since no existing mezzanine standard could meet ourrequirements, we embarked on a new mezzanine design. In order tohelp ensure acceptance from a broad industry base, Pentek createdthe mezzanine architecture to be non-proprietary, royalty-free andcompletely independent of any one processor or manufacturer.
Overview of VIM
While defining the new mezzanine, nicknamed VIM, for VelocityInterface Mezzanine, we focused on two parallel, often conflictinggoals. The immediate goal was to meet the performance needs of ourboards, with tight development and delivery schedules.
The second goal was to make decisions in implementation whichwould allow VIM to work not only with next generation TIprocessors, but also with the newest DSP and RISC devices fromother manufacturers as well, fully consistent with our openstandard mandate. Our design is shown in Figure 1.
Figure 1: The essential elements of the VIM electricalbus consist of three interfacesthe streaming parallel bus,the serial interface and the control/status interface.
VIM Streaming Parallel Bus
To decouple the processor and the streaming parallel interface,the VIM interface uses synchronous, bi-directional FIFO memories,or synch Bi-FIFOs. Synch Bi-FIFOs provide consistent,industry-standard timing and have the added benefit of bufferinginput and output data to the processor, taking optimal advantage ofthe efficient block transfers.
DMA controllers supporting the processor can easily utilize thesoftware configurable interrupt flags of the Bi-FIFOs for automaticdata transfers between the processor memory and peripheral devices,thus freeing the processor core to concentrate on more worthytasks. Any idiosyncratic timing provisions between the processorand the Bi-FIFO are transparent to the mezzanine interface. Sincemany processors already support synchronous DRAM interfaces,synchronous FIFOs are typically not difficult to handle.
There are numerous benefits to using Bi-FIFOs for the parallelinterface. With two independent ports, the Bi-FIFO supports widedisparities between mezzanine data rates and processor data rates.The mezzanine port can be clocked at any rate up to its maximum of100MHz, supporting both fast and slow peripherals as well asclocking which is either periodic, non-periodic, or “bursty”.Without the Bi-FIFO, the processor would have to try to be ready totake or deliver data at just the right time, imposing a seriousconstraint on processing tasks.
On the processor side, the Bi-FIFO can be loaded or unloadedwhenever it is convenient, usually at the end of a processing loopwhen block transfers of data make the most sense. Prudent real-timesignal processing design techniques require that the processor taskexecution time for a block of data is (at least slightly) shorterthan the time it takes to collect that block. In this way, theprocessor finishes all of its “homework” and waits (perhapsbriefly) for the next data block to become ready. Bi-FIFO bufferingembodies the ideal implementation of this approach.
Bi-FIFOs also allow slower processors to handle very high-speedstreams. A good example is the new RACE++ standard from Mercury,which specifies 32-bit words transferred at 66.66MHz. The 100MHzBi-FIFO VIM mezzanine port easily absorbs inbound RACEway packetsand allows a slower processor to subsequently unload the data at aslower rate. Likewise, the slower processor can leisurely fill theBi-FIFO with an outgoing packet and then initiate the RACEwayinterface to deliver the packet at the full rate from the VIMmezzanine port.
Table 1 summarizes the signals associated with the streamingparallel bus. All signals are single ended and compliant with TTLlevels. Note that the in/out signal direction is relative to themezzanine module.
|Data Bits||32||In/Out||Bi-directional data lines|
|FIFO Clock||1||Out||Clock for mezzanine FIFO port|
|FIFO Chip Select||1||Out||Enables the FIFO clock for reads & writes|
|FIFO Direction||1||Out||Determines the FIFO read/write model|
|FIFO Input Flags||3||In||Full, almost full, and almost empty|
|FIFO Output Flags||3||In||Empty, almost empty, and almost full|
|FIFO Reset||1||Out||Clears contents of FIFO|
|Processor Interrupt||1||In||Interrupt signal from processor|
|Mailbox Interrupt||1||In||Interrupt from FIFO mailbox|
|Mailbox Select||1||Out||Enables reads & writes to FIFO mailbox|
In addition to connecting to the VIM mezzanine module, the VIMBi-FIFO flags are available to serve as interrupt inputs to thebaseboard processor. The VIM module may also interrupt thebaseboard processor by writing to one of two special mailboxregisters contained within the Bi-FIFO.
VIM Serial Ports
The VIM serial interface supports two full duplex channels, eachwith two data lines, three clock lines and two framing signals.These seven signals provide an extremely flexible and configurableinterface to many different types of serial devices. Table 2 showseach of the lines.
|Receive Data||2||Out||One line for each of two serial ports|
|Receive Frame Sync||2||Out||''|
|Transmit Frame Sync||2||Out||''|
The receive and transmit clock lines can be configured undersoftware to support peripherals which must either receive or supplyclocks. An external clock signal may be applied to replace theprocessor's serial clock timing reference.
Many of the new processors feature integral serial ports, oftenwith sophisticated framing and TDM hardware conveniently linked toDMA controller signals. This nicely supports serial streams fromdigital telecom interfaces like E1/T1 and matches the processingfunctions of the telecom-oriented DSPs like the 'C6203 which canhandle a full T1 span of V.90 modems.
VIM Random Access Control/Status Interface
Controlling the interfaces and circuitry on the mezzanine moduleis accommodated with the VIM random access control/status bus,which closely resembles a generic microprocessor interface. Thisallows registers and other programmable resources on the module tobe mapped into a conveniently located read/write address region ofthe processor memory space.
Signals present on this portion of the VIM interface are shownbelow in Table 3. The names of most of the lines areself-explanatory.
|Data Bus||32||In/Out||Bi-directional data bus (buffered toprocessor)|
|Address Bus||16||In||Address lines (subset of processor address|
|Output Enable||1||In||Enables the module to drive data bus|
|Read Strobe||1||In||Read control signal|
|Write Enable||1||In||Write control signal|
|Ready Output||1||Out||Data transfer complete acknowledge|
|Reset||1||In||Resets or initializes the module|
|Clock Input||1||In||Processor related clock|
|Interrupt Output||1||Out||Interrupt to the processor|
|Module Present Output||1||Out||Indicates that a module is installed|
Power supply lines from the motherboard include +5 VDC and±12 VDC for powering the module. The number of pins for eachsupply and the maximum current for the module is shown in Table 4.The recommended total maximum power dissipation is 15W.
|Signal||# Pins||Total Currents|
Mechanical Aspects of VIM
Pin and socket style connectors were selected for thebaseboard/module interconnect. These compact 160- pin, four-rowconnectors occupy a minimal board footprint of 2.1 x 0.25 inchesand feature both male and female in surface mount versions,conserving valuable inner-layer printed circuit board realestate.
Figure 2: In the first implementation, the Model 4290Quad 'C6201 DSP 6U processor board, the VIM connectors werearranged in a single line parallel to the front panel. Thisarrangement gives each processor its own private VIM interface andallows module designs that span one, two, or all four processorconnection sites.
A fifth connector, of the same style as the four VIM processorconnectors, is installed near the rear of the board just in frontof the P2 backplane connector. This 200- pin interconnect includesa shared global bus as well as the 64 user-defined pins of the VMEP2 connector to support mezzanine board connections to RACEway.This fifth connector is not part of the VIM specification, and canbe specific to the needs of a particular baseboard.
Figure 3: Figure 3 shows the 4290 as viewed from the backplane connectors, with the four VIM processor connectors the globalbus and P2 connector identified. Note that the front panel issegmented, allowing two blank front panel sections to be removed tomake provisions for the front panels of VIM mezzanine modules.
VIM Module Formats
So far, several different mezzanine module form factors havebeen defined for the quad 'C6x DSP boards using the VIMspecification. These meet the various needs of a wide range ofapplications, but the first and most popular is the VIM-2 formatshown in Figure 4.
Figure 4: So far, several different mezzanine module formfactors have been defined for the quad 'C6x DSP boards using theVIM specification. These meet the various needs of a wide range ofapplications, but the VIM-2 format shown here is the first and mostpopular.
Figure 5: A front panel becomes part of the front panelof the DSP board, nesting in the same slot as the DSP board. Itattaches to two of the four processor nodes and allows twocompletely independent interfaces to each DSP through interfacecircuitry to front panel I/O functions.
Figure 6: The final assembly with two VIM-2 modulesattached to the baseboard. Note that the complete assembly occupiesonly one VMEbus slot.
Figures 7 and 8: The VIM-2 format shown in Figure 7(left) allows two different types of VIM interfaces to be combinedon the same DSP board, perhaps supporting an input function withone module and an output function with the other. Other VIMmezzanine form factors include the VIM-4, which providesconnectivity from all front panel connectors to all four DSPs asshown in Figure 8 (right).
Figures 9 and 10: Two more VIM module formats takeadvantage of the fifth global bus and P2 connector. The VIM-4Rformat shown in Figure 9 (left) supports a RACEway or VSB interfaceto all four processor nodes.
The VIM-2R in Figure 10 combines the benefits of a RACEwayinterface for two of the processors with the ability to install aVIM-2 module for other I/O functions. This configuration can takeadvantage of the inter-processor pipeline FIFOs found onhigh-performance 'C6x boards to connect high speed front panelinterfaces through a powerful DSP engine, and then out to RACEwaydevices for additional processing or storage.
Sample VIM-based Systems
Currently available VIM module functions include FPDP, RACEway,digital receivers, parallel TTL I/O, serial I/O, multi-channel A/D,and high-speed A/D converters. Each module takes advantage of thehigh-speed parallel or serial interfaces provided by VIM, whicheveris most appropriate for the module circuitry.
Figure 11: An example system shows the Model 4290 Quad'C6201 DSP processor VIM baseboard, equipped with two VIM-2modules. The entire system shown occupies only a single 6U VMEbusslot.
The first module is the Model 6216 Dual Channel Wideband DigitalReceiver, which digitizes two HF or IF band analog signals,performs a digital frequency translation and delivers a basebandsignal with Nyquist bandwidths from 1 to 32.5MHz. Two 32-bit,complex digital wideband signals are fed directly across the VIMinterface into the synchronous Bi-FIFOs on the processor baseboardand subsequently into two 'C6201s (A and B) for processing. Thecombined data rate for both channels is 260MB/sec.
Interprocessor Bi-FIFOs (identical to the VIM mezzanineBi-FIFOs) allow processors A and B to transfer data at a combinedrate of up to 800MB/sec to processors C and D for more signalprocessing. Processors C and D deliver output data to the secondmodule, a Model 6226 Dual FPDP (front panel data port) VIM-2module. Dual FPDP ports on the front panel support two 160MB/secchannels to other high-speed system components using an industrystandard interface.
VIM Specification Status
The VIM specification has been evolving for slightly more than ayear now. It has been used successfully by several customers ofPentek's 'C6x boards to design custom high-performance interfacesfor complex or proprietary functions not available as standardboard products. The benefit of being able to take advantage of themost advanced quad 'C6x processor architecture and all of thesupporting hardware and software tools available for it, offers asignificant reduction in development effort and time to market forunique or unusual applications.
Following extremely favorable initial acceptance by customers,Pentek has adopted VIM as its high-performance mezzanine of choiceas designs migrate to new processors and new module functions.Pentek intends to promote VIM as a non-proprietary, open industrystandard, incorporating third-party refinements as thespecification matures.
The VIM specification is available for viewing or downloading atwww.pentek.com/vimspecafter you register to gain access.