At the Embedded World Conference Imagination Technologies rolled out a new family of 32-bit MIPS microcontroller cores with hardware virtualization for additional security in increasing connected embedded applications.
According to Tony King-Smith, EVP marketing, Imagination, the low-power, compact, real-time MIPS M-class M51xx cores form the first group of entry-level MIPS Series5 Warrior CPUs targeting applications in industrial control, Internet of Things (IoT), wearables, cloud computing, wireless communications, automotive, storage and other applications. He said the company already has multiple licenses for the M51xx cores targeting embedded processing, automotive and beyond.
“Imagination has seen the trends leading to the need for more advanced multi-context security and multiple execution domains right across the CPU spectrum,” he said, “which is why we’re now rolling out virtualization across our entire range of MIPS Series5 CPUs, including the new entry-level M51xx family.”
The first available M-class cores are the M5100 and the M5150. The M5100 integrates a real-time execution unit and SRAM controller, and is optimized for low-cost, low-power microcontroller applications. The M5150 incorporates the same execution unit as the M5100, and adds a programmable L1 instruction and data cache controller, as well as memory management support for high-performance Linux and RTOS embedded system applications.
As with other MIPS Series5 cores, the M-class cores implement the MIPS Release 5 architecture incorporating hardware virtualization. The M51xx cores are based on the same 5-stage pipeline architecture and incorporating the comprehensive digital signal processing (DSP)/SIMD features of the previous generation MIPS microAptiv family of cores, along with the microMIPS Instruction Set Architecture (ISA) which provides up to 30% code size reduction over 32-bit only code.
King-Smith said the entire line-up of Imagination’s MIPS Series5 Warrior cores, including the entry-level M-class, the mid-range I-class and the high-end P-class cores, all incorporate hardware virtualization technology, resulting in a unified security and virtualization strategy throughout the system and across the entire SoC.
“With virtualization, multiple, unmodified, operating systems and applications can run independently and securely at the same time on a single, trusted platform,” he said, with a range of features including ability to execute multiple tasks in isolation, intelligent resource allocation across several guests, secure downloads/uploads and IP protection.
The new cores incorporate built-in prioritization virtualization mechanisms that allow support for up to seven secure/non-secure guests, without substantially affecting real-time functionality.
“In space-constrained, low-power systems such as IoT or wearable devices,” King-Smiith said, “virtualization could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another guest, under RTOS control, can provide the multimedia capabilities of the system. “
For applications that demand an even higher level of security, the new M-class cores include tamper resistant features that provide countermeasures to unwanted access to the processor operating state. A secure debug feature increases the benefit by preventing external debug probes from accessing and interrogating the core internals.
The new M51xx cores also feature a Floating Point Unit (FPU) option supporting both single and double precision instructions for improved control systems processing.