This week Imagination released a new version of the MIPS architecture that should make ARMs's goals of competing with Intel in high end heterogeneous computing applications beyond mobile phones a bit more difficult. Nor will ARM have an easy time of it in many high end consumer and mobile apps as well, if Imagination has anything to do with it.
The company has released the highly-efficient MIPS I-class I6400 Warrior CPU family, the first IP cores to combine a 64-bit architecture and hardware virtualization with scalable performance through multi-threading, multi-core and multi-cluster coherent processing.
According to Imagination's executive vice president Tony King-Smith, the 64-bit MIPS Warrior core will change the game for CPUs from mobile devices to datacenter servers
The target for the new MIPS Warrior I-class processor cores, he said, is mainstream 64-bit processing in applications including embedded, mobile, digital consumer, advanced communications, networking and storage, which he claims is the broadest set of applications ever addressed by a single MIPS core family.
“The I6400 is more efficient, flexible and scalable than the competition,” he said, and its feature set clearly lends itself to the needs of a wide range of next-generation applications including smartphones and tablets.
Among other things, the I6400 has a highly efficient, scalable 64-bit architecture that developers can use to meet the cost performance points in designs across a broad range of applications. King-Smith said it achieves over 50% higher CoreMark performance and 30% higher DMIPS compared to leading competitors in its class.
It also incorporates a feature that competitive cores, such as those from ARM, do not have, support for hardware multi-threading: up to four hardware threads per core, which King-Smith said enables execution of multiple instructions from multiple threads every clock cycle.
“Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-60% on popular industry benchmarks including SPECint and EEMBC’s CoreMark,” he said, ” and do with less than a 10% cluster area increase. “
Although the new architecture can support more, the current implementation of the I6500 core incorporates sophisticated and flexible hardare virtualization capabilities with suppor tor up to 14 secure/non-secure guest OSes.
To provide as rock-solid security as is possible, said King-Smith, the I6400 core is optimized to support multiple independent security contexts and multiple independent execution domains. “The architecture scales easilty to support simultaneous secure content delivery, secure payments, identity protection and more across multiple applications and content sources,” he said.
The I6400 features advanced power management capabilities including, among other things, the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
Recognizing the needs of many network infrastruure apps such as wireless base stations, King-Smith, said the the I6400 supports both single and double precision capabilities relevant to general computing as well as improved control systems processing.
Since mamy high end mobile apps will involve a high degree of both graphics and video data parallel processing, the I6400 features 128-bit SIMD support, with instructions defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, as well as leverage of existing code.
The SIMD in the I6400 supports a wide variety of integer (8, 16, 32 and 64-bit) and floating point (32, 64-bit) data types, making it highly efficient for many applications across audio, video, vision, and other computationally-intensive use cases.
Imagination has also put a lot of work into improving and extending the MIPS archtecture's multicore coherency capabilities through the use of a new version of its Coherency Manager fabric (Figure below ) based on a new multicore coherent interconnect architecture.
” It supports multicore configurations of up to six cores per cluster where multiple cores on a single cluster can have different synthesis targets,” he said, “and operate at different clock frequencies and voltages. “
The Coherency Manager fabric also incorporates a number of other high-performance features, including wider buses, hardware pre-fetching and lower latencies than previous generations.
Targeting a number of high end applications which require the use of hetergeneous clusters of various mixes of CPUs, GPUs, DSP and other processing elements, he said, the I6400 has been design with great care given to its multithreading capabilities in applications that require diverse combinations of threads, cores and clusters, supporting multi-cluster fabric configurations up to 64 clusters.
As a true superset of the MIPS32 architecture, the MIPS64 architecture doesn’t require separate ISAs, datapaths or mode switching, eliminating wasted silicon area and power.
One of the first projects completed through the prpl open source foundation issupport for the MIPS64 r6 architecture in the QEMU open source emulator, currently available at the GitHub web site. With QEMU, developers can get started now on developing applications and software for the 64-bit I6400.
King-Smith said Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014.