Imagination updates MIPS Aptiv cores, adds 32/64 bit Warrior -

Imagination updates MIPS Aptiv cores, adds 32/64 bit Warrior

Imagination Technology has just updated its family of MIPS Aptiv processor cores and revealed more details on a next generation 32/64 bit MIP Series 5 MIPS CPUs, code-named Warrior.

With the announcement, the company hopes to remove any doubts in developer minds about its commitment to continuing support of the MIPS architecture as well as its seriousness about competing head-to-head with both ARM and Intel for every lucrative segment of the market.

“The industry is longing for a choice in the CPU market, and we are making MIPS a clear and superior alternative in the CPU IP space,” said Hossein Yassaie, Imagination CEO.

In addition to extending each of the Aptiv MIPS families with new core configurations, later this year Imagination will start rolling out an entire generation of new MIPS CPUs, including 32-bit and 64-bit cores incorporating new architectural features.

New to the current generation of MIPS Aptiv devices is a new very small-footprint single-core version to the interAptiv family and a floating point version to the microAptiv family. According to Yassaie, the high-performance proAptiv, multi-threaded interAptiv and compact microAptiv families of cores, are all available in refined, validated configurations.

The family comes in configurations from single through to six-core versions with optional hardware floating point while the interAptiv family includes hardware multi-threading as well as single-, dual- and quad-core configurations with optional floating point. The new single-core version of interAptiv removes the extra logic associated with multi-core coherency and L2 cache controller, providing a highly-efficient, multi-threaded single-core processor.

Yassaie said the microAptiv family is available in versions targeting microcontrollers and deeply embedded processors, and now incorporates an optional hardware floating point unit for applications including electric metering and motor control.The ‘Warrior’ generation of cores will include 32-bit and 64-bit variants with a focus on matching competitive architectures across the whole range of high-end, mid-range and entry-level/microcontroller CPUs.

Cognizant of the attractiveness to developers of the instruction set compatibility of past generations of the MIPS CPUs, the ‘Warrior’ cores will provide binary compatibility from the entry-level to the high-end.

Since completing the MIPS acquisition earlier this year, he said the company has completed integration of its CPU engineering teams, nearly doubling the resources working on leading-edge MIPS CPU development.

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