Imagination's MIPS I-class I6400 CPUs boast multi-threading, multicore, multi-cluster processing -

Imagination’s MIPS I-class I6400 CPUs boast multi-threading, multicore, multi-cluster processing

The MIPS I-class I6400 CPU family from Imagination Technologies are the first IP cores to combine a 64-bit architecture and hardware virtualization with scalable performance through multi-threading, multicore and multi-cluster coherent processing. MIPS Warrior I-class processor cores target embedded, mobile, digital consumer, advanced communications, networking and storage—the broadest set of applications ever addressed by a single MIPS core family. With 64-bit, multi-threading, and multicore/multi-cluster support, the I6400 is designed to be a flexible, low-power processor architecture capable of scaling across a wide range of applications.

Main features

  • Highly efficient, scalable 64-bit performance: The I6400 will enable customers to set new price/performance points across markets. It achieves over 50% higher CoreMark performance and 30% higher DMIPS compared to leading competitors in its class (Imagination benchmark results are preliminary; competitive results are based publicly available information). The I6400 can be implemented across a very wide range of performance, power and area operating points and achieves high frequencies in aggressive implementations.
  • Hardware multi-threading: The I6400 features hardware multi-threading technology that supports up to four hardware threads per core. Imagination’s proven MIPS multi-threading technology leads to higher utilization and CPU efficiency. The simultaneous multi-threading (SMT) technology in the I6400 enables execution of multiple instructions from multiple threads every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% on popular industry benchmarks including SPECint and EEMBC’s CoreMark, with less than a 10% cluster area increase. Real-world applications such as browsers can also take significant advantage of multi-threading.
  • Hardware virtualization: The I6400 joins the entire range of MIPS Warrior cores in incorporating hardware virtualization technology, providing increased security and reliability, and enabling a unified security and virtualization strategy throughout the system and across the entire SoC. As implemented in the I6400, this includes support for up to 15 secure/non-secure guests.
  • Next-generation security: The I6400 core is optimized to support multiple independent security contexts and multiple independent execution domains. This much enhanced security capability leverages technology from Imagination and its ecosystem partners and can encompass other critical components of an SoC. The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
  • Advanced power management: With PowerGearing for MIPS, the I6400 features advanced power management capabilities. This includes the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
  • Efficient FPU: The proven hardware Floating Point Unit (FPU) in the I6400 supports both single and double precision capabilities relevant to general computing as well as improved control systems processing.
  • 128-bit SIMD: The I6400 features 128-bit SIMD support, delivering high performance and high throughput for a wide range of tasks that can exploit the efficiencies of SIMD execution in data-parallel applications. It is built on the MIPS SIMD architecture which adheres to true RISC philosophy, with instructions defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, as well as leverage of existing code. The SIMD in the I6400 supports a wide variety of integer (8-, 16-, 32- and 64-bit) and floating point (32, 64-bit) data types, making it highly efficient for many applications across audio, video, vision, and other computationally-intensive use cases.

General availability scheduled for December 2014.

More information

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