IMEC looks to exploit its technology -

IMEC looks to exploit its technology

IMEC, the Leuven-based independent microelectronics research and development centre, recently presented the results from some of its research programs.

Prototyping system for high data rates IMEC has developed a flexible hardware platform to shorten the development time that is needed to build a high data rate system demonstrator. It allows to embed prototype ASICs and to implement algorithms on flexible hardware and software.

The PICARD concepts are based on modular hardware boards and Linux driver development software. The hardware boards have high-speed data links, flexible configurable hardware, integration of prototype IP cores and built-in debug facilities. The boards are compatible with Compact-PCI.

PICARD modular hardware board concept

IMEC has identified the need to have a general platform whereby the know-how in the different domains can be reused for each demonstrator. A wireless local area Network (WLAN) has been chosen as first application to use the platform.

The PICARD hardware concepts consist of a Xilinx Virtex-II FPGA, high data rate serial links, flexible clock distribution network and a C-PCI interface. The FPGA controls all communication links between the components on the board and between other PICARD boards or C-PCI peripheral boards. To do this, the FPGA has access to all I/O pins of each component on the board. The payload communication link is based on a FIFO chain and a 'request-acknowledge' protocol to handle multi data rate transfers. A communication link between components can be enabled or bypassed.

A programmable logic analyser function on the FPGA monitors each data communication link. Besides the reusable blocks, a prototype IP core can be implemented on the multi-million gates FPGA. The communication links between the PICARD boards are implemented as gigabit per second serial links over twisted pair or coax cables. The clock distribution network allows different clocks. A board can choose its clock from a crystal, a PLL or from an external clock input and it has a clock output for another board.

The boards are compliant to the C-PCI standard and can be plugged in a standard shelf to build a system. PICARD uses Linux to ease the insertion of existing or new software modules.

While IMEC is sharing the results of this development with the members of its Industrial Affiliation Programs (IIAP), it is intended to license the PICARD design to non-members.

Baseband board of WLAN application on PICARD

CAD tool for memory optimisation

ATOMIUM, a toolbox for optimising memory I/O using geometrical models has been used with several data-dominated applications within IMEC. As it has proven to be stable and robust, it is now being made available for industrial partners in Idec's industrial affiliation program (IIAP) on MPEG-4.

Multimedia applications typically require very large data storage and transfer capacities, which are commonly found to dominate the overall system cost in terms of area, power consumption, speed, etc. To address these implementation problems, the ATOMIUM CAD tool suite has been developed to assist designers in analysing and optimising data transfer and storage bottlenecks.

ATOMIUM operates at the behavioural level of an application expressed in C. The output of the environment is a transformed C description typically leading to strongly reduced memory size and power consumption.

ATOMIUM/Analysis is the most mature component of the tool suite and supports data transfer and storage analysis as well as automatic pruning of unused C code.

A new version of the tool, ATOMIUM 1.2, also supports analysis of multithreaded applications. It supports bit fields and has improved ANSI C compliance. ATOMIUM 1.2 has been transferred to IMEC's industrial partners in its MPEG-4 IIAP and is also available via license agreement.

ATOMIUM/Memory Compaction, features automated memory size reduction by maximising the reuse of memory locations. The tool suite also includes ATOMIUM/Storage Bandwidth Optimization for exploring the effect of timing constraints on the required memory architecture.

Wireless LAN systems development

A flexible HiperLAN 2 system model from IMEC is the basis for simulating, testing, implementing and demonstrating wireless local area networks (WLANs). It allows adaption of the protocol towards different implementations of WLAN protocols and towards techniques that will further increase the network performance.

IMEC's HiperLAN 2 model specifies the medium access control (MAC) and data-link control (DLC) protocol layers. It is designed to fill a critical gap in the development of wireless communications protocols since the HiperLAN 2 standard only defines the communication rules and does not directly address critical implementation issues which influence the performance of the overall network.

It has also developed a tool that interprets and displays the binary data that is passed over the physical layer (transmitter, communication channel, receiver) in real time. A model of the physical layer is coupled to the protocol in order to simulate and verify the interaction of the physical layer with the protocol layers and the overall impact of physical layer enhancements.

RF CMOS for 5 to 20GHz applications

A three year program to develop 100nm CMOS radio-frequency (RF) modules for the 5 to 20GHz frequency range has started. It will design and fabricate RF building blocks within a 100nm CMOS technology. To this end, active devices will be optimised, passive devices including inductors, capacitors and varactors will be implemented and optimised, and building blocks for RF applications including voltage controlled oscillators and low-noise amplifiers will be designed.

ESD protection will be co-designed taking into account the parasitic effects of the ESD protection circuit in the design of the actual RF circuits, and combining this with technology optimisation to obtain optimal ESD protections without RF performance loss.

100Mbit/s turbo codec IP core

The T@MPO (Turbo coding @ Minimal POwer) intellectual property (IP) core is a full-duplex turbo encoder/decoder that will support the speed, performance and overall system requirements for a broad range of high-speed wireless and wired communications applications, including wireless local area networks digital video broadcasting and UMTS.

It implements parallel concatenated convolutional codes that allow digital transmission close to the theoretical channel capacity limit. Extremely low bit-error rates of 10-7 are achieved at signal-to-noise ratios as low as 4dB, allowing savings in transmission energy.

A parallel architecture provides a decoding speed of 100Mbit/s when using an internal clock speed of 200MHz, with a latency lower than 10ms. The IP's high scalability and efficient clock utilisation reduced the estimated decoding energy to less than 50nJ per bit.

The T@MPO core IP has a complexity of 400Kgates and uses 36Kbit internal SRAM. The device has been taped out as a 0.18mm CMOS ASIC. It is available as a knowledge transfer of a full documented design database, from high-level C descriptions down to VHDL, and the different models created during the research of the intermediate levels.

Incubation fund to ease way for spin-off

IMEC has now spun off around 20 independent companies that are commercially exploiting the technology developed at the Leuven facility. In order to ease this process it has set up an Incubation Fund to support spin-off companies during their launch phase.

During their incubation, IMEC will support entrepreneurs to prepare technology and prototypes for market launch and to set up the commercial, financial and organisational strategy of the company.

The Incubation Fund was launched with a capital of 5 million Euro. Once a project is approved by the Incubation Fund, budget will be released for setting up a company dedicated to realise the project, work out a business plan and attract the needed skills. Once these tasks are completed, the company will attract new venture capital to realise its business plan.

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