Imperas has released its first models of the Cortex family of processor cores from ARM with models of the M-series of cores added to the Open Virtual Platforms (OVP).
Included are example virtual platforms incorporating the cores and support for the cores in Imperas’ software development tools.
The models of the ARM Cortex processor cores, as well as models of the other ARM processors including the ARM7, ARM9, ARM10 and ARM11 families, work with the Imperas and OVP simulators.
All OVP processor models are instruction accurate and focus on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle.
Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The OVP simulator also has an integration with the Eclipse IDE.
The models also work with the Imperas tools for multicore software verification, analysis and debug, including tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.
Imperas is making the OVP models of the ARM Cortex M-series, including the popular ARM Cortex-M3 processor core, available now from the OVP website. Processor core models for other ARM Cortex cores will be available within the next 16 weeks.
OVP already offers ARM developers access to models of other ARM processors, including processors which utilize the v4, v5 and v6 ARM instruction sets. OVP also has reference virtual platforms incorporating the ARM cores, including bare metal platforms, a virtual platform of an Atmel AT91sam7 processor (based on an ARM7 core), and a virtual platform of the ARM IntegratorCP development board using the ARM926EJ-S.
This IntegratorCP virtual platform enables users to boot Linux in under 10 seconds on a 2GHz laptop using OVPsim. These reference platforms are available as source code, and can be modified to add or change the memory and peripheral components to customize the platfo! rm as required for software development.
Imperas' models are also being used in its collaboration with Cadence Design Systems to deliver on the EDA360 vision for System Realization. Imperas has joined the Cadence System Realization Alliance; its technology, including OVP and Imperas’ advanced software development tools, has been integrated with Cadence Incisive Enterprise Simulator and Incisive Software Extensions products, to better address the growing need for software development with robust verification.
Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “OVP, with ultrafast simulation, accelerates the development cycle and makes debug easier for software engineers. And participating in the Cadence System Realization Alliance by integrating OVP and Imperas tools with proven Cadence products helps to expand the range of solutions available to software developers.”
The processor core models and example platforms are available from the Open Virtual Platforms website.